A 32kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme in 90nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 388-622

  Chang, Ik Joon ^a   Kim, Jae Joon ^b   Park, Sang Phill ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

RADIATION HARDENING;

90-NM CMOS; BIT-INTERLEAVING; DIFFERENTIAL READS; OPERATING FREQUENCY; SOFT-ERROR TOLERANCE; SUB-THRESHOLD SRAM; WORDLINES;

CMOS INTEGRATED CIRCUITS;

EID: 49549103577     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523220     Document Type: Conference Paper

References (4)

1. B.H.Calhoun, A. Chandrakasan, "A256kb Sub-Threshold SRAM in 65nm CMOS", ISSCC Dig. Tech. Papers, pp.628-629, Feb. 2006.
2. t SRAM Employing Sense-Amplifier Redundancy", ISSCC Dig. Tech. Papers, pp.328-329, Feb. 2006.
3. T. Kim, J. Liu, J. Keane, C. H. Kim, "A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme", ISSCC Dig. Tech. Papers, pp.330-331, Feb. 2006.
4. J. Maiz, S. Hareland, K. Zhang, and P. Armstrong, "Characterization of Multi-bit Soft Error Events in Advanced SRAMs", IEDM Dig. Tech.Papers, pp.21.4.1-21.4.4, Dec. 2003.