A process-variation-tolerant dual-power-supply SRAM with 0.179μm 2 Cell in 40nm CMOS using level-programmable wordline driver

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages 458-460

  Hirabayashi, O ^a   Kawasumi, A ^a   Suzuki, A ^a   Takeyama, Y ^a   Kushida, K ^a   Sasaki, T ^a   Katayama, A ^a   Fukano, G ^a   Fujimura, Y ^a   Nakazato, T ^a   Shizuki, Y ^a   Kushiyama, N ^a   Yabe, T ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349271250     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977506     Document Type: Conference Paper

References (7)

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2. O. Takahashi, C. Adams, D. Ault, et al., "Migration of Cell Broadband Engine™ from 65nm SOI to 45nm SOI, " ISSCC Dig. Tech. Papers, pp. 86-87, Feb. 2008.
3. M.J.M. Pelgrom, A.C.J. Duinmaijer, A.P.G. Welbers, "Matching Properties of MOS Transistors, " IEEE J. Solid-State Circuits, vol.24, pp. 1433-1439, Oct. 1989.
4. Y-H. Chen, W-M. Chan, S-Y. Chou, et al., "A 0.6V 45nm Adaptive Dual-rail SRAM Compiler Circuit Design for Lower VDD-min VLSIs, " IEEE Symp. VLSI Circuits, pp. 210-211, Jun. 2008.
5. M. Khellah, N.S. Kim, Y. Ye, et al., "PVT-Variations and Supply-Noise Tolerant 45nm Dense Cache Arrays with Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi- Vcc Circuits, " Dig. Symp. IEEE Symp. VLSI Circuits, pp. 48-49, Jun. 2008.
6. K. Zhang, U. Bhattacharya, Z. Chen, et al., "A 3-GHz 70-Mb SRAM in 65-nm CMOS Technology with Integrated Column-Based Dynamic Power Supply, " IEEE J. Solid-State Circuits, vol.41, pp. 146-151, Jan. 2006.
7. M. Yabuuchi, K. Nii, Y. Tsukamoto, et al., "A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations, " ISSCC Dig. Tech. Papers, pp. 326-327, Feb. 2007