Nonvolatile magnetic flip-flop for standby-power-free SoCs

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 8, 2009, Pages 2244-2250

  Sakimura, Noboru ^a   Sugibayashi, Tadahiko ^a   Nebashi, Ryusuke ^a   Kasai, Naoki ^a  

^a NEC CORPORATION   (Japan)

Author keywords

MRAM; Nonvolatile flip flops; Standby power reduction

Indexed keywords

BIT-SHIFTS; CRITICAL APPLICATIONS; DATA BACKUPS; DESIGN LIBRARY; FUNCTIONAL PERFORMANCE; HIGH-SPEED; LSI DESIGN; MAXIMUM FREQUENCY; MRAM; NON-VOLATILE; NONVOLATILE FLIP-FLOPS; POWER DISSIPATION; POWER LINES; SPICE SIMULATIONS; STANDBY-POWER REDUCTION; SYSTEMS ON CHIPS; TEST CHIPS;

CELL MEMBRANES; MAGNETIC STORAGE; RANDOM ACCESS STORAGE; SHIFT REGISTERS; SPICE;

FLIP FLOP CIRCUITS;

EID: 68549087135     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2023192     Document Type: Article

References (16)

1. J. Lee, B. G. Nam, and H. J. Yoo, "Dynamic voltage and frequency scaling (DVFS) scheme for multi-domains power management," in IEEEA-SSCC, 2007, pp. 360-363.
2. T. Fujiyoshi, S. Shiratake, S. Nomura, T. Nishikawa, Y. Kitasho, H. Arakida, Y. Okuda, Y. Tsuboi, M. Hamada, H. Hara, T. Fujita, F. Ha-tori, T. Shimazawa, K. Yahagi, H. Takeda, M. Mrakata, F. Minami, N. Kawabe, T. Kitahara, K. Seta, M. Takahashi, Y. Owaki, and T. Furuyama, "A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic voltage/frequency scaling," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 54-62, Jan. 2006.
3. B. H. Calhoun and A. P. Chandrakasan, "Standby power reduction using dynamic voltage scaling and canary flip-flop structures," IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1504-1511, Sep. 2004.
4. K. Fukuoka, O. Ozawa, R. Mori, Y. Igarashi, T. Sasaki, T. Kuraishi, Y. Yasu, and K. Ishibashi, "A 1.92 μs-wake-up time thick-gate-oxide power switch technique for ultra low-power single-chip mobile processors," in Symp. VLSI Circuits, 2007, pp. 128-129.
5. L. T. Clark, M. Kabir, and J. E. Knudsen, "A low standby power flip-flop with reduced circuit and control complexity," in IEEE Custom Integrated Circuits Conf., 2007, pp. 571-574.
6. L. T. Clark, F. Ricci, and M. Biyani, "Low standby power state storage for sub-130-nm technologies," IEEE J. Solid-State Circuits, vol. 40, no. 2, pp. 498-506, Feb. 2005.
7. S. Masui, W. Yokozeki, M. Oura, T. Ninomiya, K. Mukaida, Y. Takayama, and T. Teramoto, "Design and applications of ferroelectric nonvolatile SRAM and flip-flop with unlimited read/program cycles and stable recall," in IEEE Custom Integrated Circuits Conf., 2003, pp. 403-406.
8. M. Ueda, T. Otsuka, K. Toyoda, K. Morimoto, and K. Morita, "A novel non-volatile flip-flop using a ferroelectric capacitor," in IEEE Int. Symp. Applications of Ferroelectrics, 2002, pp. 155-158.
9. J. DeBrosse, D. Gogl, A. Bette, H. Hoenigschmid, R. Robertazzi, C. Arndt, D. Braun, D. Casarotto, R. Havreluk, S. Lammers, W. Ober-maier, W. R. Reohr, H. Viehmann, W. J. Gallagher, and G. Muller, "A high-speed 128-Kb MRAM core for future universal memory applications," IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 678-683, Apr. 2004.
10. W. Zhao, E. Belhaire, Q. Mistral, E. Nicolle, T. Devolder, and C. Chappert, "Integration of spin-RAM technology in FPGA circuits," in Int. Conf. Solid-State and Integrated Circuit Technology, 2006, pp. 799-802.
11. N. Sakimura, T. Sugibayashi, T. Honda, H. Honjo, S. Saito, T. Suzuki, N. Ishiwata, and S. Tahara, "MRAM cell technology for over 500-MHz SoC," IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 830-838, Apr. 2007.
12. H. Honjo, R. Nebashi, T. Suzuki, S. Fukami, N. Ishiwata, T. Sugibayashi, and N. Kasai, "Performance of write-line inserted MTJ for low-write-current MRAM cell," J. Applied Physics, vol. 103, p. 07A711,2008.
13. N. Sakimura, T. Sugibayashi, R. Nebashi, H. Honjo, S. Saito, Y. Kato, and N. Kasai, "A 250-MHz 1-Mbit embedded MRAM macro using 2T1MTJ cell with bitline separation and half-pitch shift architecture," in IEEEA-SSCC, 2007, pp. 216-219.
14. R. Nebashi, N. Sakimura, T. Sugibayashi, and N. Kasai, "A 4-Mb MRAM macro comprising shared write-selection transistor cells and using a leakage-replication read scheme," in IEEE A-SSCC, 2007, pp. 220-223.
15. L.T. Clark, M.Morrow, and W.Brown, "Reverse-body bias and supply collapse for low effective standby power," IEEE Trans. VLSI Syst., vol. 12, no. 9, pp. 947-956, Sep. 2004.
16. H. Numata, T. Suzuki, N. Ohshima, S. Fukami, K. Nagahara, N. Ishiwata, and N. Kasai, "Scalable cell technology utilizing domain wall motion for high-speed MRAM," in IEEE Symp. VLSI Technology, 2007, pp. 232-233.