Magnetic tunnel junction for nonvolatile CMOS logic

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2010, Pages

  Ohno, Hideo ^a   Endoh, Tetsuo ^a   Hanyu, Takahiro ^a   Kasai, Naoki ^a   Ikeda, Shoji ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BACK END OF THE LINES; CMOS CIRCUITS; CMOS LOGIC; CURRENT STATUS; LOGIC-IN-MEMORY ARCHITECTURE; LOW POWER; MAGNETIC TUNNEL JUNCTION; NON-VOLATILE; SPINTRONIC DEVICE; STAND -ALONE;

CMOS INTEGRATED CIRCUITS; ELECTRON DEVICES; EMBEDDED SYSTEMS; MAGNETIC DEVICES; MEMORY ARCHITECTURE; RANDOM ACCESS STORAGE; TUNNEL JUNCTIONS; VLSI CIRCUITS;

LOGIC CIRCUITS;

EID: 79951826370     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2010.5703329     Document Type: Conference Paper

References (9)

1. S. Ikeda et al. IEEE Trans. Elect. Dev. 54, 991, 2007.
2. S. Fukami et al., Symp. on VLSI Tech., 230, 2009
3. T.Endoh, MRS 2010 Spring Meeting, 5-9, 2010
4. W. H. Kautz, IEEE Trans. Comput. 18, 719, 1969.
5. S. Matsunaga et al. APEX 1, 091301, 2008.
6. S. Matsunaga et al. APEX 2, 023004, 2009.
7. D. Suzuki et al. VLSI Circuit Symposium 2009
8. S. Ikeda et al., Nat. Mat. 9, 721, 2010
9. S. Fukami et al., to be presented in SSDM 2010.