A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous RAV access issues

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2007, Pages 254-255

  Ishikura, S ^a   Kurumada, M ^a   Terano, T ^a   Yamagami, Y ^a   Kotani, N ^a   Satomi, K ^a   Nii, K ^b   Yabuuchi, M ^b   Tsukamoto, Y ^b   Ohbayashi, S ^b   Oashi, T ^b   Makino, H ^b   Shinohara, H ^b   Akamatsu, H ^a  

^a PANASONIC CORPORATION   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); HIERARCHICAL SYSTEMS; THRESHOLD VOLTAGE;

HIERARCHICAL REPLICA BITLINE TECHNIQUE; LOCAL READ BIT LINE WITH DUMMY CAPACITANCE (LDC); READ END DETECTING REPLICA CIRCUIT (RER);

STATIC RANDOM ACCESS STORAGE;

EID: 39749119399     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2007.4342740     Document Type: Conference Paper

References (4)

1. M.Yabuuchi, et al., ISSCC 2007, to be published.
2. N.Shibata, et al., IEEF- JOURNALOF SOLID-STATE CIRCUITS,VOL41,N0.3, MARCH 2006
3. T.Suzuki, et al., Symp. VLSI Circuits, 2006, p. 14
4. K.Nii, et al., Symp.VLSI Circuits, 2006, p. 162