A 65nm 8T Sub-V, SRAM employing sense-amplifier redundancy

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 328-330

  Verma, Naveen ^a   Chandrakasan, Anantha P ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); REDUNDANCY;

PERIPHERAL ASSISTS; READ CURRENT;

STATIC RANDOM ACCESS STORAGE;

EID: 34548858947     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373427     Document Type: Conference Paper

References (5)

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2. E. Seevinck, F. List, and J. Lohstroh, "Static Noise Margin Analysis of MOS SRAM Cells," IEEE Journal, of Solid-State Circuits, SC-22, no. 5, pp. 748-754, Oct. 1987.
3. B. Calhoun and A. Chandrakasan, "A 256kb Sub-Threshold SRAM in 65nm CMOS," ISSCC Dig. Tech. Papers, pp. 628-629, Feb., 2006.
4. J. Chen, L. Clark, and T.-H. Chen, "An Ultra-Low-Power Memory With a Subthreshold Power Supply Voltage," IEEE J. Solid-State Circuits, vol. 41, no. 10, pp. 2344-2353, Oct., 2006.
5. K. Zhang, K Hose, V. De, et al., "The Scaling of Data Sensing Schemes for High-Speed Cache Design in Sub-0.18μm Technologies," Symp. VLSI Circuits, pp. 226-227, Jun., 2000.