A sub-600mV, fluctuation tolerant 65nm CMOS SRAM array with dynamic cell biasing

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2007, Pages 78-79

  Bhavnagarwala, Azeez ^a   Kosonocky, Stephen ^a   Chan, Yuen ^b   Stawiasz, Kevin ^a   Srinivasan, Uma ^b   Kowalczyk, Steve ^a   Ziegler, Matt ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELL LEAKAGE; DYNAMIC CELL BIASING;

CMOS INTEGRATED CIRCUITS; LEAKAGE CURRENTS; TRANSISTORS;

STATIC RANDOM ACCESS STORAGE;

EID: 39749136138     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2007.4342773     Document Type: Conference Paper

References (9)