A 100MHz to IGHz, 0.35V to 1.5V supply 256 × 64 SRAM block using symmetrized 9T SRAM cell with controlled read

Proceedings of the IEEE International Frequency Control Symposium and Exposition

Volumn , Issue , 2008, Pages 560-565

  Verkila, Satish Anand ^a   Bondada, Siva Kumar ^a   Amrutur, Bharadwaj S ^a  

^a INDIAN INSTITUTE OF SCIENCE   (India)

Author keywords

[No Author keywords available]

Indexed keywords

65NM TECHNOLOGY; ACTIVE MODE (AM); ADDRESS DECODERS; BIT LINE (BL); BODY BIASING; CUT-OFF; DYNAMIC VOLTAGES; FREQUENCY RANGING; INTERNATIONAL CONFERENCES; LEAKAGE ENERGIES; LOW-VOLTAGE (LV); NMOS TRANSISTORS; NOISE MARGIN (NM); OPERATING FREQUENCIES; REDUCING POWER; SRAM CELLS; STANDBY MODES; STATIC NOISE MARGIN (SNM); TOTAL ENERGIES; VLSI DESIGNS; VOLTAGE DROPS;

CELLS; CMOS INTEGRATED CIRCUITS;

STATIC RANDOM ACCESS STORAGE;

EID: 47649109815     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSI.2008.89     Document Type: Conference Paper

References (12)

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