-
1
-
-
61449113156
-
A process variation tolerant embedded split-gate Flash memory using pre-stable current sensing scheme
-
March
-
M.-F. Chang and S.-J. Shen, "A process variation tolerant embedded split-gate Flash memory using pre-stable current sensing scheme," IEEE J. Solid-State Circuits, vol. 44, no. 3, pp.987-994, March 2009.
-
(2009)
IEEE J. Solid-State Circuits
, vol.44
, Issue.3
, pp. 987-994
-
-
Chang, M.-F.1
Shen, S.-J.2
-
2
-
-
0033280083
-
High speed cascode sensing scheme for 1.0 V contact-programming Mask ROM
-
R. Sasagawa, I. Fukushi, M. Hamaminato, and S. Kawashima, "High speed cascode sensing scheme for 1.0 V contact-programming Mask ROM," Symposium on VLSI Circuits Dig. Tech. Papers, pp. 95-96, 1999.
-
(1999)
Symposium on VLSI Circuits Dig. Tech. Papers
, pp. 95-96
-
-
Sasagawa, R.1
Fukushi, I.2
Hamaminato, M.3
Kawashima, S.4
-
3
-
-
31644438897
-
A full code-pattern coverage high-speed embedded ROM using dynamic virtual guardian technique
-
Feb.
-
M.-F. Chang, L.-Y. Chiou, and K.-A. Wen, "A full code-pattern coverage high-speed embedded ROM using dynamic virtual guardian technique," IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 496-506, Feb. 2006.
-
(2006)
IEEE J. Solid-State Circuits
, vol.41
, Issue.2
, pp. 496-506
-
-
Chang, M.-F.1
Chiou, L.-Y.2
Wen, K.-A.3
-
4
-
-
67349087909
-
Analysis and reduction of supply noise fluctuations induced by embedded ROM
-
June
-
M.-F. Chang, and S.-M. Yang, "Analysis and reduction of supply noise fluctuations induced by embedded ROM," IEEE Tran. on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 6, pp. 758-769, June 2009.
-
(2009)
IEEE Tran. on Very Large Scale Integration (VLSI) Systems
, vol.17
, Issue.6
, pp. 758-769
-
-
Chang, M.-F.1
Yang, S.-M.2
-
5
-
-
57849131821
-
Robust ultralow voltage ROM design
-
Sep.
-
M. Seok, S. Hanson, J.-S. Seo, D. Sylvester, and D. Blaauw, "Robust ultralow voltage ROM design," IEEE CICC Dig. Tech. Papers, pp. 423-426, Sep. 2008.
-
(2008)
IEEE CICC Dig. Tech. Papers
, pp. 423-426
-
-
Seok, M.1
Hanson, S.2
Seo, J.-S.3
Sylvester, D.4
Blaauw, D.5
-
7
-
-
0034315851
-
A dynamic voltage scaled microprocessor system
-
Nov
-
T. D. Burd, et al.,"A dynamic voltage scaled microprocessor system," IEEE J. of Solid-State Circuits, no. 11, pp.1571-1580, Nov 2000.
-
(2000)
IEEE J. of Solid-State Circuits
, Issue.11
, pp. 1571-1580
-
-
Burd, T.D.1
-
8
-
-
0036858657
-
A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling
-
Nov.
-
K. J. Nowka, et al., "A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1441-1447, Nov. 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, Issue.11
, pp. 1441-1447
-
-
Nowka, K.J.1
-
10
-
-
34548830136
-
A sub-200mV 6T SRAM in 0.13μm CMOS
-
Feb.
-
B. Zhai, D. Blaauw, D. Sylvester, S. Hanson, "A sub-200mV 6T SRAM in 0.13μm CMOS,," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 332-333, Feb. 2007.
-
(2007)
IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers
, pp. 332-333
-
-
Zhai, B.1
Blaauw, D.2
Sylvester, D.3
Hanson, S.4
-
12
-
-
34047110771
-
Crosstalk-insensitive via-programming ROMs using content-aware design framework
-
June
-
M.-F. Chang, L.-Y. Chiou, and K.-A. Wen, "Crosstalk-insensitive via-programming ROMs using content-aware design framework," IEEE Transactions on Circuits and Systems II, vol. 53, issue 6, pp. 443-447, June 2006.
-
(2006)
IEEE Transactions on Circuits and Systems II
, vol.53
, Issue.6
, pp. 443-447
-
-
Chang, M.-F.1
Chiou, L.-Y.2
Wen, K.-A.3
-
13
-
-
31344479086
-
Enhanced Write Performance of a 64-Mb Phase-Change Random Access Memory
-
January
-
H.-R. Oh, et al., "Enhanced Write Performance of a 64-Mb Phase-Change Random Access Memory," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp.122-126, January 2006.
-
(2006)
IEEE J. Solid-State Circuits
, vol.41
, Issue.1
, pp. 122-126
-
-
Oh, H.-R.1
-
14
-
-
85008054314
-
A 90 nm 1.8 V 512 Mb Diode-Switch PRAM with 266 MB/s Read Throughput
-
January
-
K.-J. Lee, et al., "A 90 nm 1.8 V 512 Mb Diode-Switch PRAM with 266 MB/s Read Throughput," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp.150-162, January 2008.
-
(2008)
IEEE J. Solid-State Circuits
, vol.43
, Issue.1
, pp. 150-162
-
-
Lee, K.-J.1
-
15
-
-
34548861504
-
A 512kB embedded Phase Change Memory with 416kB/s write through at 100uA cell write current
-
Feb.
-
S. Hanzawa, et al., "A 512kB embedded Phase Change Memory with 416kB/s write through at 100uA cell write current," ISSCC, pp. 474-475, Feb. 2007.
-
(2007)
ISSCC
, pp. 474-475
-
-
Hanzawa, S.1
-
16
-
-
77952185915
-
A 90nm 4Mb embedded Phase-Change memory with 1.2V 12ns read access time and 1MB/s write throughput
-
Feb.
-
G. D. Sandre, et al., "A 90nm 4Mb embedded Phase-Change memory with 1.2V 12ns read access time and 1MB/s write throughput", ISSCC Dig. Tech. Papers, pp. 268-269, Feb. 2010.
-
(2010)
ISSCC Dig. Tech. Papers
, pp. 268-269
-
-
Sandre, G.D.1
-
17
-
-
77957879314
-
MLC PRAM with SLC write-speed and robust read scheme
-
June
-
Y. N. Hwang, et al., "MLC PRAM with SLC write-speed and robust read scheme," Symp. VLSI Tech. Dig. Tech. Papers, pp. 201-202, June 2010.
-
(2010)
Symp. VLSI Tech. Dig. Tech. Papers
, pp. 201-202
-
-
Hwang, Y.N.1
-
18
-
-
85008008190
-
2 Mb SPRAM (Spin-Transfer Torque RAM) with Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read
-
January
-
T. Kawahara, et al.,"2 Mb SPRAM (Spin-Transfer Torque RAM) with Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read "IEEE J. Solid-State Circuits, vol. 43, no. 1, pp.109-120, January 2008.
-
(2008)
IEEE J. Solid-State Circuits
, vol.43
, Issue.1
, pp. 109-120
-
-
Kawahara, T.1
-
19
-
-
77950229376
-
A 32-Mb SPRAM with 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme
-
April
-
R. Takemura et al.,"A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme," IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 869-879, April 2010.
-
(2010)
IEEE J. Solid-State Circuits
, vol.45
, Issue.4
, pp. 869-879
-
-
Takemura, R.1
-
21
-
-
0038528647
-
A 1-Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects
-
May
-
M. Durlam, et al., "A 1-Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects," IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 769-773, May 2007.
-
(2007)
IEEE J. Solid-State Circuits
, vol.38
, Issue.5
, pp. 769-773
-
-
Durlam, M.1
-
22
-
-
33947624246
-
A Nonvolatile 2-Mbit CBRAM Memory Core Featuring Advanced Read and Program Control
-
April
-
S. Dietrich et al., "A Nonvolatile 2-Mbit CBRAM Memory Core Featuring Advanced Read and Program Control," IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 839-845, April 2007.
-
(2007)
IEEE J. Solid-State Circuits
, vol.42
, Issue.4
, pp. 839-845
-
-
Dietrich, S.1
-
23
-
-
39749096089
-
Time discrete voltage sensing and iterative programming control for a 4F2 multilevel CBRAM
-
P. Schrogmeier, et al. "Time discrete voltage sensing and iterative programming control for a 4F2 multilevel CBRAM," Symp. VLSI Circuits Dig. Tech. Papers, June 2007.
-
Symp. VLSI Circuits Dig. Tech. Papers, June 2007
-
-
Schrogmeier, P.1
-
24
-
-
21644443347
-
Highly scalable non-volatile resistive memory using sinple binary oxide driven by asymmetric unipolar voltage pulses
-
Dec.
-
I. G. Baek, et al., "Highly scalable non-volatile resistive memory using sinple binary oxide driven by asymmetric unipolar voltage pulses," IEDM Dig. Tech. Paper, pp. 587, Dec. 2004.
-
(2004)
IEDM Dig. Tech. Paper
, pp. 587
-
-
Baek, I.G.1
-
25
-
-
33847722993
-
Non-volatile resistive switching for advanced memory applications
-
Dec.
-
A. Chen, et al., "Non-volatile resistive switching for advanced memory applications," IEDM Dig. Tech. Papers, p.746, Dec. 2005.
-
(2005)
IEDM Dig. Tech. Papers
, pp. 746
-
-
Chen, A.1
-
26
-
-
43549102297
-
Excellent uniformity and reproducible resistance switching characteristics of doped binary metal oxides for non-volatile resistance memory applications
-
Dec.
-
D. Lee, et al., "Excellent uniformity and reproducible resistance switching characteristics of doped binary metal oxides for non-volatile resistance memory applications," IEDM Dig. Tech. Papers, pp. 797, Dec. 2006.
-
(2006)
IEDM Dig. Tech. Papers
, pp. 797
-
-
Lee, D.1
-
27
-
-
67949097936
-
Low Power and High Speed Bipolar Switching with A Thin Reactive Ti Buffer Layer in Robust HfO2 Base RRAM
-
Dec.
-
H.-Y. Lee, et al., "Low Power and High Speed Bipolar Switching with A Thin Reactive Ti Buffer Layer in Robust HfO2 Base RRAM", IEDM Dig. Tech. Paper, pp. 297-300, Dec. 2008.
-
(2008)
IEDM Dig. Tech. Paper
, pp. 297-300
-
-
Lee, H.-Y.1
-
28
-
-
70449393681
-
A 5ns Fast Write Multi-Level Non-Volatile 1 K bits RRAM Memory with Advance Write Scheme
-
June
-
S.-S. Sheu, et al.,"A 5ns Fast Write Multi-Level Non-Volatile 1 K bits RRAM Memory with Advance Write Scheme," IEEE Symp. VLSI Circuits Dig. Tech. Papers, pp. 82-83, June, 2009.
-
(2009)
IEEE Symp. VLSI Circuits Dig. Tech. Papers
, pp. 82-83
-
-
Sheu, S.-S.1
-
29
-
-
0023437909
-
Static-noise margin analysis of MOS SRAM cells
-
Oct.
-
E. Seevinck, F. J. List, and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells," IEEE J. Solid-State Circuits, vol. 22, no. 5, pp.748-754, Oct. 1987.
-
(1987)
IEEE J. Solid-State Circuits
, vol.22
, Issue.5
, pp. 748-754
-
-
Seevinck, E.1
List, F.J.2
Lohstroh, J.3
-
30
-
-
25144518593
-
Process variation in embedded memories:failure analysis and variation aware architecture
-
Sep.
-
A. Agarwal, B. C. Paul, S. Mukhopadhyay, and K. Roy, "Process variation in embedded memories:failure analysis and variation aware architecture," IEEE J. Solid-State Circuits, vol. 40, no. 9, pp.1804-1814, Sep. 2005.
-
(2005)
IEEE J. Solid-State Circuits
, vol.40
, Issue.9
, pp. 1804-1814
-
-
Agarwal, A.1
Paul, B.C.2
Mukhopadhyay, S.3
Roy, K.4
-
31
-
-
33746369469
-
Static noise margin variation for sub-threshold SRAM in 65-nm CMOS
-
July
-
B.H. Calhoun and A. P. Chandrakasan, "Static noise margin variation for sub-threshold SRAM in 65-nm CMOS," IEEE J. Solid-State Circuits, vol. 41, no. 7, pp. 1673-1679, July 2006.
-
(2006)
IEEE J. Solid-State Circuits
, vol.41
, Issue.7
, pp. 1673-1679
-
-
Calhoun, B.H.1
Chandrakasan, A.P.2
-
32
-
-
73249152995
-
A 1.6 GB/s DDR2 128 Mb chain FeRAM with scalable octal bitline and sensing schemes
-
Jan.
-
H. Shiga et al., "A 1.6 GB/s DDR2 128 Mb chain FeRAM with scalable octal bitline and sensing schemes," IEEE J. Solid-State Circuits, vol. 45, no. 1, pp. 142-152, Jan. 2010.
-
(2010)
IEEE J. Solid-State Circuits
, vol.45
, Issue.1
, pp. 142-152
-
-
Shiga, H.1
-
33
-
-
33750592887
-
Three-Dimensional Integration Technology Based on Wafer Bonding with Vertical Buried Interconnections
-
Nov.
-
M. Koyanagi, et al., "Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections" IEEE Transactions on Electron Devices, Issue 11, pp. 2799-2808 Nov. 2006.
-
(2006)
IEEE Transactions on Electron Devices
, Issue.11
, pp. 2799-2808
-
-
Koyanagi, M.1
-
34
-
-
0034453365
-
Three-dimensional shared memory fabricated using wafer stacking technology
-
K. W. Lee, et al., "Three-dimensional shared memory fabricated using wafer stacking technology" International Electron Device Meeting (IEDM), pp. 165-168, 2000.
-
(2000)
International Electron Device Meeting (IEDM)
, pp. 165-168
-
-
Lee, K.W.1
-
37
-
-
21644471419
-
Highly area efficient and cost effective double stacked S^3 (stacked single-crystal Si) peripheral CMOS SSTFT and SRAM cell technology for 512M bit density SRAM
-
S.-M. Jung, et al., "Highly area efficient and cost effective double stacked S^3 (stacked single-crystal Si) peripheral CMOS SSTFT and SRAM cell technology for 512M bit density SRAM," International Electron Device Meeting (IEDM), pp. 265-268, 2004.
-
(2004)
International Electron Device Meeting (IEDM)
, pp. 265-268
-
-
Jung, S.-M.1
-
39
-
-
49549094516
-
A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure
-
Feb.
-
K. T. Park, et al., "A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 510-632, Feb. 2008.
-
(2008)
IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers
, pp. 510-632
-
-
Park, K.T.1
-
41
-
-
68549087135
-
Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs
-
Aug.
-
N. Sakimura et al., "Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs," IEEE J. Solid-State Circuits, vol. 44, no. 8, pp. 2244-2250, Aug. 2009.
-
(2009)
IEEE J. Solid-State Circuits
, vol.44
, Issue.8
, pp. 2244-2250
-
-
Sakimura, N.1
-
42
-
-
0035273822
-
NV-SRAM: A nonvolatile SRAM with backup ferroelectric capacitors
-
Mar.
-
T. Miwa, et al., "NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors" IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 522-527, Mar. 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, Issue.3
, pp. 522-527
-
-
Miwa, T.1
-
45
-
-
77957980630
-
A Low Store Energy, Low VDDmin, Nonvolatile 8T2R SRAM with 3D Stacked RRAM Devices for Low Power Mobile Applications
-
June
-
P. F. Chiu, M.-F. Chang, et al., "A Low Store Energy, Low VDDmin, Nonvolatile 8T2R SRAM with 3D Stacked RRAM Devices for Low Power Mobile Applications," Symposium on VLSI Circuits Dig. Tech. Papers, pp. 229-230, June 2010.
-
(2010)
Symposium on VLSI Circuits Dig. Tech. Papers
, pp. 229-230
-
-
Chiu, P.F.1
Chang, M.-F.2
|