Implementation of the CELL broadband engine™ in a 65nm SOI technology featuring dual-supply SRAM arrays supporting 6GHz at 1.3V

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 322-324

  Pille, J ^a   Adams, C ^a   Christensen, T ^a   Cottier, S ^b   Ehrenreich, S ^a   Kono, F ^c   Nelson, D ^a   Takahashi, O ^b   Tokito, S ^d   Torreiter, O ^a   Wagner, O ^a   Wendel, D ^a  

^a IBM   (Germany)

^b IBM   (United States)

^c TOSHIBA CORPORATION   (Japan)

^d SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BROADBAND NETWORKS; COMPUTER HARDWARE; ELECTRIC POTENTIAL; ELECTRIC POWER UTILIZATION;

CELL BROADBAND ENGINE; OPERATING VOLTAGE; SRAM ARRAYS;

STATIC RANDOM ACCESS STORAGE;

EID: 34548845553     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373424     Document Type: Conference Paper

References (4)

1. D. Pham, S. Asano, M. Bolliger, et al., "The Design and Implementation of A First-Generation CELL Processor," ISSCC Dig. Tech. Papers, pp. 184-185, Feb., 2005.
2. D. Pham, T. Aipperspach, D. Boerstler, et al., "Overview of the Architecture, Circuit Design and Physical Implementation of a First-Generation CELL Processor," IEEE J. Solid-State Circuits, vol. 41, pp. 1692-1706, Aug., 2006
3. J. Davis, J. Plass, P. Bunce, et al., "A 5.6GHz 64kB Dual-Read Data Cache for the POWER6™ Processor," ISSCC Dig. Tech. Papers, pp. 622-623, Feb., 2006.
4. K. Zhang, K Hose, V. De, et al., "The Scaling of Data Sensing for High Speed Cache Designs in Sub-0.18mm Technologies," Symp. on VLSI, pp. 226-227, Jun., 2000.