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Volumn 31, Issue 12, 1996, Pages 1862-1872

A 200 mW, 1 Msample/s, 16-b pipelined A/D converter with on-chip 32-b microcontroller

Author keywords

[No Author keywords available]

Indexed keywords

CALIBRATION; CMOS INTEGRATED CIRCUITS; CONTROL EQUIPMENT; CONTROL NONLINEARITIES; CROSSTALK; ERROR CORRECTION; MICROPROCESSOR CHIPS; PIPELINE PROCESSING SYSTEMS;

EID: 0030394188     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.545806     Document Type: Article
Times cited : (39)

References (14)
  • 1
    • 3643146675 scopus 로고
    • Sipex Corporation data sheet, SP9490
    • Sipex Corporation data sheet, SP9490, "16-b, 1 MHz sampling ADC," 1991.
    • (1991) 16-b, 1 MHz Sampling ADC
  • 3
    • 0027853599 scopus 로고
    • A 15-b 1 Msample/s digitally self-calibrated pipeline ADC
    • Dec.
    • A. N. Karanicolas, H. S. Lee, and K. L. Bacrania, "A 15-b 1 Msample/s digitally self-calibrated pipeline ADC," IEEE J. Solid-State Circuits, vol. 28, pp. 1207-1215, Dec. 1993.
    • (1993) IEEE J. Solid-State Circuits , vol.28 , pp. 1207-1215
    • Karanicolas, A.N.1    Lee, H.S.2    Bacrania, K.L.3
  • 4
    • 0026141224 scopus 로고
    • A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3 μm CMOS
    • Apr.
    • Y. M. Lin, B. Kim, and P. R. Gray, "A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3 μm CMOS," IEEE J. Solid-State Circuits, vol. 26, pp. 628-635, Apr. 1991.
    • (1991) IEEE J. Solid-State Circuits , vol.26 , pp. 628-635
    • Lin, Y.M.1    Kim, B.2    Gray, P.R.3
  • 5
    • 0028417146 scopus 로고
    • A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC
    • Apr.
    • H. S. Lee, "A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC," IEEE J. Solid-State Circuits, vol. 29, pp. 509-515, Apr. 1994.
    • (1994) IEEE J. Solid-State Circuits , vol.29 , pp. 509-515
    • Lee, H.S.1
  • 6
    • 0030106088 scopus 로고    scopus 로고
    • A power optimized 13-b 5 Msample/s pipelined analog-to-digital converter in 1.2 μm CMOS
    • Mar.
    • D. Cline and P. R. Gray, "A power optimized 13-b 5 Msample/s pipelined analog-to-digital converter in 1.2 μm CMOS," IEEE J. Solid State Circuits, vol. 31, pp. 294-303, Mar. 1996.
    • (1996) IEEE J. Solid State Circuits , vol.31 , pp. 294-303
    • Cline, D.1    Gray, P.R.2
  • 8
    • 0030081881 scopus 로고    scopus 로고
    • Monolithic low-power 16-b 1 Msample/s self-calibrating pipeline ADC
    • Feb.
    • M. K. Mayes and S. W. Chin, "Monolithic low-power 16-b 1 Msample/s self-calibrating pipeline ADC," in IEEE ISSCC, Feb. 1996, pp. 312-313.
    • (1996) IEEE ISSCC , pp. 312-313
    • Mayes, M.K.1    Chin, S.W.2
  • 11
    • 0024931690 scopus 로고
    • A multistep A/D converter family with efficient architecture
    • Dec.
    • M. K. Mayes and S. W. Chin, "A multistep A/D converter family with efficient architecture," IEEE J. Solid-State Circuits, vol. 24, pp. 1492-1497, Dec. 1989.
    • (1989) IEEE J. Solid-State Circuits , vol.24 , pp. 1492-1497
    • Mayes, M.K.1    Chin, S.W.2
  • 12
    • 0029269932 scopus 로고
    • A 10 b, 20 Msample/s, 35 mW pipeline A/D converter
    • Mar.
    • T. Byunghak and R. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipeline A/D converter," IEEE J. Solid-State Circuits, vol. 30, pp. 166-172, Mar. 1995.
    • (1995) IEEE J. Solid-State Circuits , vol.30 , pp. 166-172
    • Byunghak, T.1    Gray, R.R.2
  • 13
    • 3643107093 scopus 로고    scopus 로고
    • U.S. Patent #4 336 526
    • B. Weir, U.S. Patent #4 336 526.
    • Weir, B.1
  • 14
    • 0027576336 scopus 로고
    • Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits
    • Apr.
    • D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, "Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits," IEEE J. Solid-State Circuits, vol. 28, no. 4. Apr. 1993.
    • (1993) IEEE J. Solid-State Circuits , vol.28 , Issue.4
    • Su, D.K.1    Loinaz, M.J.2    Masui, S.3    Wooley, B.A.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.