A 1.8-V 67mW 10-bit 100MSPS pipelined ADC using time-shifted CDS technique

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2003, Pages 413-416

  Li, Jipeng ^a   Moon, Un Ku ^a  

^a Oregon State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFICATION; BANDWIDTH; CMOS INTEGRATED CIRCUITS; ELECTRIC INVERTERS; ELECTRIC POWER SUPPLIES TO APPARATUS; INVERSE PROBLEMS; MULTIPLYING CIRCUITS; OPERATIONAL AMPLIFIERS; VOLTAGE CONTROL;

CORRELATED DOUBLE SAMPLING TECHNIQUE; POWER CONSUMPTION; PSEUDO-DIFFERENTIAL ARCHITECTURE;

ANALOG TO DIGITAL CONVERSION;

EID: 0242443698     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. S. Yoo et al., "A 10b 150MS/s 123 mW CMOS Pipelined ADC," ISSCC Dig. Tech. Papers, pp. 326-327, Feb 2003.
2. B. Min et al., "A 69mW 10b 80MS/s pipelined Pipelined ADC," ISSCC Dig. Tech. Papers, pp. 324-325, Feb 2003.
3. J. Li and U. Moon, "High-speed Pipelined ADC Using Time-Shifted CDS Technique," IEEE Int. Symp. Circuits Syst., vol. I, pp. 90-912, May 2002.
4. K. Nagaraj, "Switched-Capacitor Circuits with Reduced Sensitivity to Amplifier Gain," IEEE Trans. Circuits Syst., vol. CAS-34, pp. 571-574, May 1987.
5. A.A. Ali and K. Nagaraj, "Correction of Operational Amplifier Gain Error in Pipelined A/D Converters," IEEE Int. Symp. Circuits Syst., pp. 1.568-1.571, May 2001.
6. M. Waltari and K. Halonen, "Timing skew insensitive switching for double sampled circuits," IEEE Int. Symp. Circuits Syst., vol. II, pp. 61-64, May 1999.