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Volumn , Issue CIRCUITS SYMP., 2004, Pages 436-439

0.9V 12mW 2MSPS algorithmic ADC with 81dB SFDR

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CALIBRATION; CAPACITORS; DEGRADATION; ELECTRIC POTENTIAL; ERROR ANALYSIS; FABRICATION; FEEDBACK; LEAKAGE CURRENTS; PERFORMANCE; SIGNAL DISTORTION; SPURIOUS SIGNAL NOISE; TOPOLOGY;

EID: 4544284883     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (5)

References (11)
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  • 2
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    • Keskin, M.1    Moon, U.2    Ternes, G.3
  • 3
    • 0041695216 scopus 로고    scopus 로고
    • A 1.4-V 10-bit 25-MS/s pipelined ADC using opamp-reset switching technique
    • Aug.
    • D. Chang, L. Wu, and U. Moon, "A 1.4-V 10-bit 25-MS/s pipelined ADC using opamp-reset switching technique," IEEE J. Solid-Sate Circuits, vol. 38, pp. 1401-1404, Aug. 2003.
    • (2003) IEEE J. Solid-sate Circuits , vol.38 , pp. 1401-1404
    • Chang, D.1    Wu, L.2    Moon, U.3
  • 4
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    • A 0.9V 9mW 1MSPS digitally calibrated ADC with 75dB SFDR
    • Jun.
    • D. Chang and U. Moon, "A 0.9V 9mW 1MSPS digitally calibrated ADC with 75dB SFDR," IEEE Sym. VLSI circuit, pp. 461-464, Jun. 2003.
    • (2003) IEEE Sym. VLSI Circuit , pp. 461-464
    • Chang, D.1    Moon, U.2
  • 5
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    • 1.2-V CMOS switched-capacitor circuits
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    • Wu, J.1    Chang, Y.2    Chang, K.3
  • 6
    • 0032664038 scopus 로고    scopus 로고
    • A 1.5-V 10-bit 14.3MS/S CMOS pipeline ADC
    • May
    • A. Abo and P. Gray, "A 1.5-V 10-bit 14.3MS/S CMOS pipeline ADC," IEEE J. Solid-Sate Circuits, vol. 34, pp. 599-606, May 1999.
    • (1999) IEEE J. Solid-sate Circuits , vol.34 , pp. 599-606
    • Abo, A.1    Gray, P.2
  • 7
    • 0035273851 scopus 로고    scopus 로고
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    • Mar.
    • M. Dessouky and A. Kaiser, "Very low-voltage digital-audio modulator with 88-dB dynamic range using local switch boot-strapping," IEEE J. Solid-Sate Circuits, vol. 36, pp. 349-355, Mar. 2001.
    • (2001) IEEE J. Solid-sate Circuits , vol.36 , pp. 349-355
    • Dessouky, M.1    Kaiser, A.2
  • 8
    • 0141954044 scopus 로고    scopus 로고
    • Background calibration techniques for multi-stage pipelined ADCs with digital redundancy
    • Sep.
    • J. Li and U. Moon, "Background calibration techniques for multi-stage pipelined ADCs with digital redundancy," IEEE Trans. Circuits Syst. II, vol. 50, No. 9, pp. 531-538, Sep. 2003.
    • (2003) IEEE Trans. Circuits Syst. II , vol.50 , Issue.9 , pp. 531-538
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  • 9
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    • Dec.
    • O. Erdogan et al., "A 12-b digital-background-calibrated algorithmic ADC with -90dB THD," IEEE J. Solid-State Circuits, vol. 34, pp. 1812-1820, Dec. 1999.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.