A 600 MSPS 8-bit folding ADC in 0.18μm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2004, Pages 424-427

  Wang, Zheng Yu ^a   Pan, Hui ^b   Chang, Chung Ming ^a   Yu, Hai Rong ^a   Chang, M Frank ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b BROADCOM CORPORATION   (United States)

Author keywords

A D converter; Capacitive averaging; Distributed track and holds; Folding and interpolation

Indexed keywords

A/D CONVERTER; CAPACITIVE AVERAGING; DISTRIBUTED TRACK-AND-HOLDS; FOLDING AND INTERPOLATION;

AMPLIFIERS (ELECTRONIC); CAPACITORS; DIGITAL COMMUNICATION SYSTEMS; ELECTRIC CONVERTERS; ELECTRIC POTENTIAL; INTERPOLATION; OPTIMIZATION; SIGNAL DISTORTION; SIGNAL TO NOISE RATIO; THERMOMETERS;

CMOS INTEGRATED CIRCUITS;

EID: 4544256284     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. A.G.W. Venes and van-de-Plassche. R. J. "An 80MHz 80mW 8b CMOS Folding A/D Converter with Distributed T/H Preprocessing," ISSCC Dig., pp318-319, Feb. 1996.
2. K.Kattmarm and J.Barrow, "A Technique for Reducing Differential Nonlinearity Errors in Flash A/D Converters," ISSCC Dig. Tech. Papers, pp170-171, Feb. 1991.
3. Kusumoto, K. and Matsuzawa, A. "A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC," JSSC, vol.28, pp. 1200-1206, Dec. 1993.
4. Hui Pan and Abidi, A. A. "Spatial Filtering in Flash A/D Converters," Circuits and System II: Analog and Digital Signal Processing, IEEE transactions on, pp424-436, Aug. 2003.