A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 12, 2004, Pages 2139-2151

  Chiu, Yun ^a   Gray, Paul R ^a   Nikolić, Borivoje ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Analog integrated circuits; Capacitor mismatch; Comparator sharing; Discrete time common mode voltage regulation; Early comparison; Low power; Low voltage; Nested CMOS gain boosting; Opamp sharing; Passive capacitor error averaging

Indexed keywords

BANDWIDTH; CAPACITORS; CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ERROR ANALYSIS; OPTIMIZATION; SIGNAL TO NOISE RATIO; SWITCHES; TRANSISTORS;

ANALOG INTEGRATED CIRCUITS; CAPACITOR MISMATCH; COMPARATOR SHARING; DISCRETE-TIME COMMON-MODE VOLTAGE REGULATION; EARLY COMPARISON; LOW POWER; LOW VOLTAGE; NESTED CMOS GAIN BOOSTING; OPAMP SHARING; PASSIVE CAPACITOR ERROR-AVERAGING;

ANALOG TO DIGITAL CONVERSION;

EID: 10444266682     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.836232     Document Type: Conference Paper

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