A 150MS/s 8b 71mW time-interleaved ADC in 0.18μm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Limotyrakis, Sotirios ^a   Kulchycki, Scott D ^a   Su, David ^a   Wooley, Bruce A ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ETHERNET; ETHERNET PROTOCOL; PIPELINE STAGES; POWER DISSIPATION;

BANDWIDTH; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; FUNCTIONS; NETWORK PROTOCOLS; SPURIOUS SIGNAL NOISE; TRANSCONDUCTANCE; WIRELESS TELECOMMUNICATION SYSTEMS;

ANALOG TO DIGITAL CONVERSION;

EID: 2442657679     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. A. M. Abo et. al., "A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter," IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999.
2. K. Nagaraj et.al., "Efficient 6-bit A/D Converter Using 1-bit Folding Front End," IEEE J. Solid-State Circuits, vol. 34, no.8, pp. 1056-1062, Aug. 1999.