Area-Efficient self-calibration technique for pipe-lined algorithmic a/d converters

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 43, Issue 7, 1996, Pages 540-544

  Nagaraj, K ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CALIBRATION; CMOS INTEGRATED CIRCUITS; ELECTRIC ATTENUATORS; MOSFET DEVICES; PARALLEL ALGORITHMS;

AREA EFFICIENT SELF CALIBRATION TECHNIQUE; CALIBRATION CIRCUIT; REFERENCE VOLTAGE;

ANALOG TO DIGITAL CONVERSION;

EID: 0030190925     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.508433     Document Type: Article

References (7)

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2. P. W, Li et al., A ratio independent algorithmic analog-to-digital conversion technique, IEEE J. Solid-Stale Circuits, vol. SC-19, pp. 1138-1143, Dec. 1984.
3. B.-S. Song et al., A 12 bit 1-Msamples/s capacitor error-averaging pipelined A/D converter, IEEE J. Solid-State Circuits, vol. 23, pp. 1324-1333, Dec. 1988.
4. H. Ohara el al, A CMOS programmable self-calibrating 13-bit eighlchannel data acquisition peripheral. IEEE J. Solid-Slate Circuits, vol. SC-22, pp. 930-938, Dec. 1987.
5. Y. M. Lin et al., A 13-n 2.5 MHz self-calibrated pipelined A/D converter in 3m process, IEEE J. Solid-Slate Circuits, vol. 26, pp. 628-636, Apr. 1991.
6. H.-S. Lee, A 12-b 600 Ks/s digitally self-calibrated pipelined algorithmic ADC, IEEE}. Solid-Stale Circuits, vol. 29, pp. 509-515, Apr. 1994.
7. C.-C. Shih and P. R. Gray, Reference refreshing cyclic analog-todigital and digital-to-analog converters, IEEE J. Solid-State Circuits. vol. SC-21, pp. 544-554, Aug. 1986.