An 80MHz 4x oversampled cascaded ΔΣ-pipelined ADC with 75dB DR and 87dB SFDR

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Bosi, Alessandro ^a   Panigada, Andrea ^a   Cesura, Giovanni ^a   Castello, Rinaldo ^b  

^a STMICROELECTRONICS   (Italy)

^b UNIVERSITY OF PAVIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144436399     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. P. Balmelli, Q. Huang, "A 25MS/S 14b 200mW ΔΣ Modulator in 0.18μm CMOS," ISSCC Dig. Tech. Papers, pp. 74-75, Feb., 2004.
2. L. Breems, "A Cascaded Continuos-Time ΔΣ Modulator with 67dB Dynamic Range in 10MHz Bandwidth," ISSCC Dig. Tech. Papers, pp. 72-73, Feb., 2004.
3. P. Kiss et al., "Adaptive Digital Correction of Analog Errors in MASH ADC's-Part II: Correction Using Test-Signal Injection," IEEE T. Circuits and Syst. II, vol. 47, no. 7, pp. 629-638, July, 2000.
4. I. Galton, "Digital Cancellation of D/A Converter Noise in Pipelined A/D Converters," IEEE T. Circuits and Syst. II, vol. 47, no. 3, pp. 185-196, March, 2000.