A 12b 80MS/s pipelined ADC with bootstrapped digital calibration

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Grace, Carl R ^a,b   Hurst, Paul J ^a   Lewis, Stephen H ^a  

^a University of California   (United States)

^b Rockwell Semiconductor Systems   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

RADIX CONVERTERS; RESIDUE GAIN ERRORS; SAMPLE AND HOLD AMPLIFIERS (SHA);

CALIBRATION; CMOS INTEGRATED CIRCUITS; DIGITAL TO ANALOG CONVERSION; ESTIMATION; INSTRUMENT ERRORS; MICROPROCESSOR CHIPS; RANDOM ACCESS STORAGE;

ANALOG TO DIGITAL CONVERSION;

EID: 2442650652     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. A. Karanicolas et al., "A 15-b 1MSample/s Digitally Self-Calibrated Pipeline ADC," IEEE J. Solid-State Circuits, pp. 1207-1215, Dec. 1993.
2. B. Murmann and B. Boser, "A 12b 75MS/S Pipelined ADC Using Open-Loop Residue Amplification," ISSCC Dig. Tick. Papers, pp. 328-329, Feb. 2003.
3. L. Singer et al., "A 12b 65MSample/s CMOS ADC with 82dB SFDR at 120MHz," ISSCCDig. Tech. Papers, pp. 38-39, Feb. 2000.
4. E. B. Blecker et al., "Digital Background Calibration of an Algorithmic Analog-to-Digital Converter Using a Simplified Queue," IEEE J. Solid-State Circuits, pp. 1059-1082, June 2003.
5. X. Wang et al. "A 12-bit 20-MS/s Pipelined ADC with Nested Digital Background Calibration," IEEE Custom Integrated Circuits Conference Digest, pp. 409-412, Sept. 2003.
6. R. J. Van De Plassche, "Dynamic Element Matching for High-Accuracy Monolithic D/A Converters," IEEE J. Solid-State Circuits, pp. 795-800, Dec. 1976.