A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 μm CMOS

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 3, 1996, Pages 294-303

  Cline, David W ^a,b,c,d,e,f   Gray, Paul R ^{a,b,g,h,i,j,k,l}  

^a IEEE

^b UNIVERSITY OF CALIFORNIA   (United States)

^c Level One Communications   (United States)

^d MISSOURI UNIVERSITY OF SCIENCE AND TECHNOLOGY   (United States)

^e UNIVERSITY OF CALIFORNIA   (United States)

^f University of Arizona ^*

^g UNIVERSITY OF ARIZONA   (United States)

^h Research and Development Laboratory   (United States)

ⁱ Electronics Research Laboratory   (Netherlands)

^j EECS Dept for Computer Resources

^k EECS Department

^l NATIONAL ACADEMY OF ENGINEERING   (United States)

more..

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ENERGY DISSIPATION; INTEGRATED CIRCUIT MANUFACTURE; OPERATIONAL AMPLIFIERS; OPTIMIZATION; SIGNAL DISTORTION; SIGNAL TO NOISE RATIO; TRANSFER FUNCTIONS;

DIFFERENTIAL NONLINEARITY; INTEGRAL NONLINEARITY; PIPELINED ANALOG TO DIGITAL CONVERTERS; POWER DISSIPATION MINIMIZATION; SIGNAL TO NOISE PLUS DISTORTION RATIO;

POWER CONVERTERS;

EID: 0030106088     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.494191     Document Type: Article

References (16)

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