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Volumn , Issue , 2003, Pages 409-412

A 12-bit 20-MS/s pipelined ADC with nested digital background calibration

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CALCULATIONS; CALIBRATION; CAPACITORS; CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; ERROR ANALYSIS; OPERATIONAL AMPLIFIERS;

EID: 0242696104     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (30)

References (15)
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  • 4
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    • J. Ming, and S. H. Lewis, "An 8-bit 80-Msample/s Pipelined Analog-to-Digital Converter With Background Calibration," IEEE J. Solid-State Circuits, pp. 1489-1497, Oct. 2001.
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    • Ming, J.1    Lewis, S.H.2
  • 5
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    • A CMOS programmable self-calibrating 13-bit eight-channel data acquisition peripheral
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    • H. Ohara, H. X. Ngo, M. J. Armstrong, C. F. Rahim, and P. R. Gray, "A CMOS Programmable Self-Calibrating 13-bit Eight-Channel Data Acquisition Peripheral," IEEE J. Solid-State Circuits, pp. 930-938, Dec. 1987.
    • (1987) IEEE J. Solid-State Circuits , pp. 930-938
    • Ohara, H.1    Ngo, H.X.2    Armstrong, M.J.3    Rahim, C.F.4    Gray, P.R.5
  • 6
    • 0028417146 scopus 로고
    • A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC
    • Apr.
    • H. S. Lee, "A 12-b 600 ks/s Digitally Self-Calibrated Pipelined Algorithmic ADC," IEEE J. Solid-State Circuits, pp. 509-515, Apr. 1994.
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    • Lee, H.S.1
  • 7
    • 18544399632 scopus 로고    scopus 로고
    • A 12-b digital-background-calibrated algorithmic ADC with -90-dB THD
    • Dec.
    • O. E. Erdoǧan, P. J. Hurst, and S. H. Lewis, "A 12-b Digital-Background-Calibrated Algorithmic ADC with -90-dB THD," IEEE J. Solid-State Circuits, pp. 1812-1820, Dec. 1999.
    • (1999) IEEE J. Solid-State Circuits , pp. 1812-1820
    • Erdoǧan, O.E.1    Hurst, P.J.2    Lewis, S.H.3
  • 8
    • 0027853599 scopus 로고
    • A 15-b 1Msample/s digitally self-calibrated pipeline ADC
    • Dec.
    • A. Karanicolas, H.-S. Lee, and K. Bacrania, "A 15-b 1Msample/s digitally self-calibrated pipeline ADC," IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1207-1215, Dec. 1993.
    • (1993) IEEE J. Solid-State Circuits , vol.28 , Issue.12 , pp. 1207-1215
    • Karanicolas, A.1    Lee, H.-S.2    Bacrania, K.3
  • 10
    • 0027810431 scopus 로고
    • Efficient circuit configurations for algorithmic analog to digital converters
    • Dec.
    • K. Nagaraj, "Efficient Circuit Configurations for Algorithmic Analog to Digital Converters," IEEE Trans. on Circuits and Systems II, pp. 777-785, Dec. 1993.
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    • Nagaraj, K.1
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  • 13
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    • A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input
    • Dec.
    • W. Yang, D. Kelly, I. Mehr, M. T. Sayuk, and L. Singer, "A 3-V 340-mW 14-b 75-Msample/s CMOS ADC With 85-dB SFDR at Nyquist Input," IEEE J. Solid-State Circuits, pp. 1931-1936, Dec., 2001.
    • (2001) IEEE J. Solid-State Circuits , pp. 1931-1936
    • Yang, W.1    Kelly, D.2    Mehr, I.3    Sayuk, M.T.4    Singer, L.5
  • 14
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    • T. B. Cho, and P. R. Gray, "A 10 b, 20 Msample/s, 35 mW Pipeline A/D Converter," IEEE J. Solid-State Circuits, pp. 166-172, Mar. 1995.
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  • 15
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    • D. W. Cline and P. R. Gray, "A Power Optimized 13-b 5 Msamples/s Pipelined Analog-to-Digital Converter in 1.2 μm CMOS," IEEE J. Solid-State Circuits, pp. 294-303, Mar. 1996.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.