SCOPUS 정보 검색 플랫폼

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2004, Pages 276-279

A 600MS/s, 5-bit pipelined Analog-to-Digital Converter for serial-link applications

(2) Varzaghani, Aida a Yang, Chih Kong Ken a

a UNIVERSITY OF CALIFORNIA (United States)

Author keywords

Analog to digital converter; CMOS; Effective number of bits; Pipeline; Resolution; Signal to noise ratio

Indexed keywords

BANDWIDTH; CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; FREQUENCIES; OPTICAL RESOLVING POWER; PIPELINES; POWER SUPPLY CIRCUITS; SAMPLING; SIGNAL TO NOISE RATIO; TUNING;

DIGITAL EQUILIZATION; DIGITAL TUNING; EFFECTIVE NUMBER OF BITS (ENOB); SAMPLING FREQUENCY;

ANALOG TO DIGITAL CONVERSION;

EID: 4544256290 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper

Times cited : (25)

References (7)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.