3.3-V 12-b 50-MS/s A/D converter in 0.6-μm CMOS with over 80-dB SFDR

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 12, 2000, Pages 1769-1780

  Pan, Hui ^a   Segami, Masahiro ^b   Choi, Michael ^c   Cao, Jing ^d   Abidi, Asad A ^c  

^a BROADCOM CORPORATION   (United States)

^b YOKOGAWA ELECTRIC CORPORATION   (Japan)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d NONE

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL FILTERS; HARMONIC ANALYSIS;

SPATIAL FILTERS;

ANALOG TO DIGITAL CONVERSION;

EID: 0034480240     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.890290     Document Type: Article

References (60)

1. T. Gratzek, B. Brannon, J. Camp, and F. Murden, "A new paradigm for base station receivers: High IF sampling + digital filtering," in 1997 IEEE Radio Frequency Integrated Circuits Symp., June 1997, pp. 143-146.
2. -, "ADCs for digital receivers: The whole world tunes in," in 1996 IEEE MTT-S Dig., pp. 1335-1338.
3. D. B. Chester, D. H. Damerow, and C. Olmstead, "Analog to digital converter requirements and implementations for narrowband channelization applications," in IEEE Int. Conf. Acoustics, Speech and Signal Processing, vol. 4, Mar. 1992, pp. 325-328.
4. F. Murden and R. Gosser, "12-b 50-Msample/s two-stage A/D converter," in ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 1995, pp. 278-279.
5. Analog Devices, AD9042 Data Sheet, 1996.
6. P. Vorenkamp and R. Roovers, "A 12-b 60-MSample/s cascaded folding and interpolating ADC," IEEE J. Solid-State Circuits, vol. 32, pp. 1876-1886, Dec. 1997.
7. D. Birdsall and A. Kuckreja, "A 12-bit, 65 MSPS BiCMOS ADC for cellular base-station applications," in Proc. 1998 Bipolar/BiCMOS Circuits and Technology Meeting, Sept. 1998, pp. 43-46.
8. A. G. Clavier, P. F. Panter, and D. D. Grieg, "Distortion in a pulse count modulation system," AIEE Trans., vol. 66, pp. 989-1005, 1947.
9. D. R. Martin and D. J. Secor, "High-speed analog-to-digital converters in communication systems: Terminology, architecture, theory and performance," TRW Electronics Systems Group, Redondo Beach, CA, Nov. 1981.
10. W. T. Colleran, "A 10-bit 100-MS/s A/D converter using folding, interpolating, and analog encoding," Ph.D. dissertation, Univ. California, Los Angeles, CA, Dec. 1993.
11. H. Pan, "A 3.3-V 12-b 50-MS/s A/D converter in 0.6-μm CMOS with over 80-dB SFDR," Ph.D. dissertation, UCLA, Dec. 1999.
12. W. R. Bennett, "Spectra of quantized signals," Bell Syst. Tech. J., vol. 27, pp. 446-472, July 1948.
13. A. Gersho, "Principle of quantization," IEEE Trans. Circuits Syst., vol. CAS-25, pp. 427-436, July 1978.
14. R. M. Gray, "Quantization noise spectra," IEEE Trans. Inform. Theory, vol. 36, pp. 1220-1244, Nov. 1990.
15. R. M. Gray and D. L. Neuhoff, "Quantization," IEEE Trans. Inform. Theory, vol. 44, pp. 1-63, Oct. 1998.
16. S. H. Lewis and P. R. Gray, "A pipelined 5-Msample/s 9-bit analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 22, pp. 954-961, Dec. 1987.
17. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. 24, pp. 1433-1440, Oct. 1989.
18. M. J. M. Pelgrom and M. Vertregt, "CMOS technology for mixed signal ICs," Solid-State Electron., vol. 41, pp. 967-974, July 1997.
19. S. H. Lewis et al., "A 20-b 20-Msample/s analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 27, pp. 351-358, Mar. 1992.
20. H.-S. Lee, D. A. Hodges, and P. R. Gray, "A self-calibrating 12-b CMOS A/D converter," IEEE J. Solid-State Circuits, vol. SC-19, pp. 813-819, Dec. 1984.
21. Y. M. Lin, B. Kim, and P. R. Gray, "A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-μm CMOS," IEEE J. Solid-State Circuits, vol. 26, pp. 628-636, Dec. 1991.
22. S.-H. Lee and B.-S. Song, "Digital-domain calibration of multistep analog-to-digital converters," IEEE J. Solid-State Circuits, vol. 27, pp. 1679-1688, Dec. 1992.
23. M. de Wit, K.-S. Tan, and R. K. Hester, "A low-power 12-b analog-to-digital converter with on-chip precision trimming," IEEE J. Solid-State Circuits, vol. 28, pp. 455-461, Dec. 1993.
24. E. G. Soenen and R. L. Geiger, "An architecture and an algorithm for fully digital correction of monolithic pipelined ADCs," IEEE Trans. Circuits Syst. II, vol. 42, pp. 143-153, Dec. 1995.
25. I. E. Opris, L. D. Lewicki, and B. C. Wong, "A single-ended 12-bit 10 Msample/s self-calibrating piepline A/D converter," IEEE J. Solid-State Circuits, vol. 33, pp. 1898-1903, Dec. 1998.
26. R. E. J. van de Grift, I. W. J. M. Rutten, and M. van der Veen, "An 8-bit video ADC incorporating folding and interpolation techniques," IEEE J. Solid-State Circuits, vol. SC-22, pp. 944-953, Dec. 1987.
27. R. J. van de Plassche and P. Baltus, "An 8-bit 100-MHz full-Nyquist analog-to-digital converter," IEEE J Solid-State Circuits, vol. 23, pp. 1334-1344, Dec. 1988.
28. W. T. Colleran and A. A. Abidi, "A 10-b 75-MHz two-stage pipelined bipolar A/D converter," IEEE J. Solid-State Circuits, vol. 28, pp. 1187-1199, Dec. 1993.
29. R. Roovers and M. Steyaert, "Design of CMOS A/D converters with folding and/or interpolating techniques," in Advanced A-D and D-A Conversion Techniques and Their Applications, July 6-8, 1994, pp. 76-81.
30. B. Nauta and A. G. W. Venes, "A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter," IEEE J. Solid-State Circuits, vol. 32, pp. 1302-1308, Dec. 1995.
31. A. G. W. Venes and R. J. van de Plassche, "An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing," IEEE J. Solid-State Circuits, vol. 31, pp. 1846-1853, Dec. 1996.
32. M. Flynn and B. Sheahan, "A 400MSample/s 6-b CMOS folding and interpolating ADC," in ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 1998, pp. 150-151.
33. 2," IEEE J. Solid-State Circuits, vol. 32, pp. 1887-1895, Dec. 1997.
34. K. Kattmann and J. Barrow, "A technique for reducing differential non-linearity errors in flash A/D converters," in ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 1991, pp. 170-171.
35. J. L. White and A. A. Abidi, "Active resistor networks as 2D sampled data filters," IEEE Trans. Circuits Syst. I: Fundamental Theory and Applications, vol. 39, pp. 724-733, Sept. 1992.
36. B.D. Smith, "An unusual analog-digital conversion method," IRE Trans. Instrum. Meas., pp. 155-160, June 1956.
37. J. D. Edson and H. H. Henning, "Broadband codecs for an experimental 224 Mb/s PCM terminal," Bell Syst. Tech. J., pp. 1887-1940, Nov. 1965.
38. A. Arbel and R. Kurz, "Fast ADC," IEEE Trans. Nucl. Sci., vol. NS-22, pp. 446-451, Feb. 1975.
39. U. Fieldler and D. Seitzer, "A high-speed 8-bit A/D converter based on a gray-code multiple folding circuit," IEEE J. Solid-State Circuits, vol. SC-14, pp. 547-551, June 1979.
40. R. J. van de Plassche and R. E. J. van de Grift, "A high-speed 7 bit A/D converter," IEEE J. Solid-State Circuits, vol. SC-14, pp. 938-943, Dec. 1979.
41. R. E. J. van de Grift and R. J. van de Plassche, "A monolithic 8-bit video A/D converter," IEEE J. Solid-State Circuits, vol. SC-19, pp. 374-378, June 1984.
42. T. Ando, A. B. Fowler, and F. Stern, "Electronic properties of two-dimensional systems," Rev. Mod. Phys., vol. 54, pp. 437-672, 1982.
43. G. S. Gildenblat and C.-L. Huang, "Engineering model of inversion channel mobility for 60-300 K temperature range," Electron. Lett., vol. 25, pp. 634-636, May 1989.
44. M. de Wit, "Sample and hold circuitry and methods," U.S. Patent 5170075, Texas Instruments Inc., Dec. 8, 1992.
45. A. M. Abo and P. R. Gray, "A 1.5-V 10-bit 14.3-MS/s CMOS pipeline analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 34, pp. 599-606, May 1999.
46. K. Bult and G. J. G. M. Geelen, "A fast-settling CMOS op amp for SC circuits with 90-dB dc gain," IEEE J. Solid-State Circuits, vol. 25, pp. 1379-1384, Dec. 1990.
47. T. B. Cho and P. R. Gray, "A 10-b 20-Msample/s 35-mW pipeline A/D converter," IEEE J. Solid-State Circuits, vol. 30, pp. 166-172, Mar. 1995.
48. +-silicon capacitor structures for single-poly analog CMOS and BiCMOS processes," IEEE Trans. Electron Dev., vol. 36, pp. 1620-1628, Sept. 1989.
49. C. W. Mangelsdorf, "A 400-MHz input flash converter with error correction," IEEE J. Solid-State Circuits, vol. 25, pp. 184-191, Feb. 1990.
50. K. Y. Kim, N. Kusayanagi, and A. A. Abidi, "A 10-b 100-MS/s CMOS A/D converter," IEEE J. Solid-State Circuits, vol. 32, pp. 302-311, Mar. 1997.
51. C. S. G. Conroy, W. A. Lane, and M. A. Moran, "Statistical design techniques for D/A converters," IEEE J. Solid-State Circuits, vol. 24, pp. 1118-1128, Aug. 1989.
52. M. J. McNutt, S. LeMarquis, and J. L. Dunkley, "Systematic capacitance matching errors and corrective layout procedures," IEEE J. Solid-State Circuits, vol. 29, pp. 611-616, May 1994.
53. H. P. Tuinhout, H. Elzinga, J. T. Brugman, and F. Postma, "The floating gate measurement technique for characterization of capacitor matching," IEEE Trans. Semicond. Manufact., vol. 9, pp. 2-8, Feb. 1996.
54. P. Carbone and D. Petri, "Effective frequency-domain ADC testing," IEEE Trans. Circuits Syst. II, vol. 47, pp. 660-663, July 2000.
55. L. R. Carley, "A noise shaping coder topology for 15+-bit converters," IEEE J. Solid-State Circuits, vol. 24, pp. 267-273, Apr. 1989.
56. B. H. Leung and S. Sutarja, "Multibit D S A/D converter incorporating a novel class of dynamic element matching techniques," IEEE Trans. Circuits Syst. II, vol. 39, pp. 35-51, Jan. 1992.
57. R. T. Baird and T. S. Fiez, "Linearity enhancement of multibit ΔΣ A/D and D/A converters using data-weighted averaging," IEEE Trans. Circuits Syst. II, vol. 42, pp. 753-762, Dec. 1995.
58. R. Radke, A. Eshraghi, and T. S. Fiez, "A spurious-free delta-sigma DAC using rotated data weighted averaging," in Proc. IEEE 1999 Custom Integrated Circuits Conf., May 1999, pp. 125-128.
59. R. Adams, K. Q. Nguyen, and K. Sweetland, "A 113-dB SNR oversampling DAC with segmented noise-shaped scrambling," IEEE J. Solid-State Circuits, vol. 33, pp. 1871-1878, Dec. 1998.
60. I. Galton, "Digital cancellation of D/A converter noise in pipelined A/D converters," IEEE Trans. Circuits Syst. II, to be published.