A 2GS/s 6b ADC in 0.18μm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Jiang, Xicheng ^a,b   Wang, Zhengyu ^a   Chang, M Frank ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b BROADCOM CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; BANDWIDTH; BUFFER AMPLIFIERS; COMPUTER SIMULATION; GAIN MEASUREMENT; MONTE CARLO METHODS; NYQUIST DIAGRAMS; OPTIMIZATION; PRINTED CIRCUIT BOARDS; SIGNAL TO NOISE RATIO; TIMING DEVICES;

CIRCUIT BANDWIDTH; DATA COMMUNICATION LINKS; DIRECT DIE TO BOARD WIRE BONDING; DISK DRIVE READ CHANNELS; NYQUIST INPUT FREQUENCIES;

CMOS INTEGRATED CIRCUITS;

EID: 0038645290     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. K. Kattmann, J. Barrow, "A Technique for Reducing Differential Nonlinearity Errors in Flash A/D Converters" ISSCC Digest of Technical Papers, pp. 170-171, 1991.
2. 2," ISSCC Digest of Technical Papers, pp. 136-137, 1997.
3. H. Pan, et al., "A 3.3V, 12b, 50MSample/s A/D Converter in 0.6mm CMOS with over 80dB SFDR," ISSCC Digest of Technical Papers, pp. 40-41, 2000.
4. M. Choi, A.A. Abidi, "A 6b 1.3 GSample/s A/D Converter in 0.35 mm CMOS," ISSCC Digest of Technical Papers, pp. 126-127, 2001.
5. P. Scholtens and M. Vertregt, "A 6b 1.6 GSamples/s Flash ADC in 0.18 mm CMOS using Averaging Termination," ISSCC Digest of Technical Papers, pp. 128-129, 2002.