메뉴 건너뛰기




Volumn 21, Issue 9, 2000, Pages 397-399

Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC POTENTIAL; ELECTROSTATICS;

EID: 0034258881     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (126)

References (10)
  • 1
    • 0026896303 scopus 로고
    • Scaling the Si MOSFET: From bulk to SOI to bulk
    • July
    • R.-H. Yan, A. Ourmazd, and K. F. Lee, "Scaling the Si MOSFET: From bulk to SOI to bulk," IEEE Trans. Electron Devices, vol. 39, pp. 1704-1710, July 1992.
    • (1992) IEEE Trans. Electron Devices , vol.39 , pp. 1704-1710
    • Yan, R.-H.1    Ourmazd, A.2    Lee, K.F.3
  • 2
    • 0027847411 scopus 로고
    • Scaling theory for double-gate SOI MOSFETs
    • Dec
    • K. Suzuki et al., "Scaling theory for double-gate SOI MOSFETs," IEEE Trans. Electron Devices, vol. 40, pp. 2326-2329, Dec. 1993.
    • (1993) IEEE Trans. Electron Devices , vol.40 , pp. 2326-2329
    • Suzuki, K.1
  • 3
    • 0032187666 scopus 로고    scopus 로고
    • Generalized scale length for two-dimensional effects in MOSFETs
    • Oct
    • D. J. Frank, Y. Taur, and H.-S. P. Wong, "Generalized scale length for two-dimensional effects in MOSFETs," IEEE Electron Device Lett., vol. 19, pp. 385-387, Oct. 1998.
    • (1998) IEEE Electron Device Lett. , vol.19 , pp. 385-387
    • Frank, D.J.1    Taur, Y.2    Wong, H.-S.P.3
  • 4
    • 0032314539 scopus 로고    scopus 로고
    • Evanescent-mode analysis of short-channel effects in fully depleted SOI and related MOSFETs
    • D. Monroe and J. M. Hergenrother, "Evanescent-mode analysis of short-channel effects in fully depleted SOI and related MOSFETs," in Proc. Int. IEEE SOI Conf., Oct. 1998, pp. 157-158.
    • (1998) Proc. Int. IEEE SOI Conf., Oct. , pp. 157-158
    • Monroe And, D.1    Hergenrother, J.M.2
  • 5
    • 0025486394 scopus 로고
    • Two-dimensional analytic modeling of very thin SOI MOSFETs
    • Sept
    • J. C. S. Woo, K. W. Terrill, and P. K. Vasudev, "Two-dimensional analytic modeling of very thin SOI MOSFETs," IEEE Trans. Electron Devices, vol. 37, pp. 1999-2005, Sept. 1990.
    • (1990) IEEE Trans. Electron Devices , vol.37 , pp. 1999-2005
    • Woo, J.C.S.1    Terrill, K.W.2    Vasudev, P.K.3
  • 7
    • 34047164707 scopus 로고
    • Three-dimensional characterization of bipolar transistors in a submicron BiCMOS technology using integrated process and device simulation
    • M. R. Pinto et al., "Three-dimensional characterization of bipolar transistors in a submicron BiCMOS technology using integrated process and device simulation," in IEDM Tech. Dig, 1992, pp. 923-926.
    • (1992) IEDM Tech. Dig , pp. 923-926
    • Pinto, M.R.1
  • 8
    • 0026122410 scopus 로고
    • Impact of surrounding gate transistor (SGT) for ultra-high-density LSIs
    • Mar
    • H. Takato et al., "Impact of surrounding gate transistor (SGT) for ultra-high-density LSIs," IEEE Trans. Electron Devices, vol. 38, pp. 573-577, Mar. 1991.
    • (1991) IEEE Trans. Electron Devices , vol.38 , pp. 573-577
    • Takato, H.1
  • 10
    • 0031079417 scopus 로고    scopus 로고
    • Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFETs
    • Feb
    • C. P. Auth and J. D. Plummer, "Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFETs," IEEE Electron Device Lett., vol. 18, pp. 74-76, Feb. 1997.
    • (1997) IEEE Electron Device Lett. , vol.18 , pp. 74-76
    • Auth, C.P.1    Plummer, J.D.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.