Impact of extrinsic and intrinsic parameter variations on CMOS system on a chip performance

Proceedings - 12th Annual IEEE International ASIC/SOC Conference

Volumn , Issue , 1999, Pages 267-271

  Bowman, Keith A ^a   Tang, Xinghai ^a   Eble, John C ^b   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; ELECTRIC LOSSES; GATES (TRANSISTOR); SYSTEM-ON-CHIP;

CRITICAL PATH DELAYS; EFFECTIVE CHANNEL LENGTH; EXTRINSIC PARAMETER; FUTURE TECHNOLOGIES; GATE OXIDE THICKNESS; HIGH-PERFORMANCE CMOS; INTRINSIC PARAMETERS; STANDARD DEVIATION;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 33646929026     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASIC.1999.806517     Document Type: Conference Paper

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