20-nm physical gate length NMOSFET featuring 1.2 nm gate oxide, shallow implanted source and drain and BF2 pockets

IEEE Electron Device Letters

Volumn 21, Issue 4, 2000, Pages 173-175

  Deleonibus, S ^a   Caillat, C ^a   Guegan, G ^a   Heitzmann, M ^a   Nier, M E ^b   Tedesco, S ^a   Dal'zotto, B ^a   Martin, F ^a   Mur, P ^a   Papon, A M ^a   Lecarval, G ^a   Biswas, S ^c   Souil, D ^d  

^a CEA LETI   (France)

^b STMICROELECTRONICS   (France)

^c BRUNEL UNIVERSITY   (United Kingdom)

^d NONE

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON BEAM LITHOGRAPHY; ELLIPSOMETRY; GATES (TRANSISTOR); INTEGRATED CIRCUIT MANUFACTURE; ION IMPLANTATION; MASKS; REACTIVE ION ETCHING; SEMICONDUCTING BORON; SEMICONDUCTOR GROWTH; SILICON WAFERS; THERMOOXIDATION; TRANSMISSION ELECTRON MICROSCOPY;

DRAIN POCKETS; GATE OXIDE; HARD MASK ETCHING TECHNIQUE; METALLURGICAL LENGTH; SHALLOW IMPLANTED SOURCE; TUNNELING DIELECTRIC;

MOSFET DEVICES;

EID: 0033887194     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.830972     Document Type: Article

References (12)

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