Highly scalable and fully logic compatible SRAM cell technology with metal damascene process and W local interconnect

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1998, Pages 64-65

  Inohara, M ^a   Oyamatsu, H ^a   Unno, Y ^a   Fukaura, Y ^a   Goto, S ^a   Egi, Y ^a   Kinugawa, M ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT;

STATIC RANDOM ACCESS MEMORY (SRAM);

RANDOM ACCESS STORAGE;

EID: 0031632523     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)