Robust digital VLSI using carbon nanotubes

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 31, Issue 4, 2012, Pages 453-471

  Zhang, Jie ^a   Lin, Albert ^a   Patil, Nishant ^a   Wei, Hai ^a   Wei, Lan ^b   Philip Wong, H S ^a   Mitra, Subhasish ^a  

^a Stanford University   (United States)

^b Massachusetts Institute of Technology Cambridge   (United States)

Author keywords

Carbon nanotube; imperfection; modeling; monolithic 3 D; nanotechnology; variation

Indexed keywords

CARBON NANOTUBE FIELD-EFFECT TRANSISTORS; CARBON NANOTUBES (CNTS); DESIGN TOOL; ELECTRONIC SYSTEMS; ENERGY EFFICIENT; FUNDAMENTAL LIMITATIONS; MONOLITHIC 3-D; PERFORMANCE VARIATIONS; PROBABILISTIC ANALYSIS; PROCESS IMPROVEMENT; PROCESSING TECHNIQUE; VARIATION; VERY LARGE-SCALE INTEGRATION;

ALIGNMENT; CARBON NANOTUBES; DEFECTS; DIGITAL CIRCUITS; ENERGY EFFICIENCY; MODELS; NANOTECHNOLOGY; THREE DIMENSIONAL;

VLSI CIRCUITS;

EID: 84859048309     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2012.2187527     Document Type: Article

References (126)

1. A. Agarwal, K. Chopra, D. Blaauw, and V. Zolotov, "Circuit optimization using statistical static timing analysis," in Proc. Des. Automat. Conf., 2005, pp. 321-324. (Pubitemid 41675453)
2. H. Ago, S. Imamura, T. Okazaki, T. Saito, M. Yumura, and M. Tsuji, "CVD growth of single-walled carbon nanotubes with narrow diameter distribution over Fe/MgO catalyst and their fluorescence spectroscopy," J. Phys. Chem. B, vol. 109, no. 20, pp. 10035-10041, May 2005. (Pubitemid 40786067)
3. D. Akinwande, J. Liang, S. Chong, Y. Nishi, and H.-S. P. Wong, "Analytical ballistic theory of carbon nanotube transistors: Experimental validation, device physics, parameter extraction, and performance projection," J. Appl. Phys., vol. 104, no. 12, pp. 1-7, 2008.
4. J. Appenzeller "Carbon nanotubes for high-performance electronicsprogress and prospect," Proc. IEEE, vol. 96, no. 2, pp. 201-211, Feb. 2008.
5. R. Ashraf, R. K. Nain, M. Chrzanowska-Jeske, and S. G. Narendra, "Design methodology for carbon nanotube based circuits in the presence of metallic tubes," in Proc. Int. Symp. Nanoscale Architect., 2010, pp. 71-76.
6. P. Avouris, Z. Chen, and V. Perebeinos, "Carbon-based electronics," Nat. Nanotechnol., vol. 2, no. 10, pp. 605-615, 2007. (Pubitemid 47525190)
7. A. Bachtold, P. Hadley, T. Nakanishi, and C. Dekker, "Logic circuits with carbon nanotube transistors," Science, vol. 294, no. 5545, pp. 1317-1320, 2001. (Pubitemid 33063092)
8. A. Balijepalli, S. Sinha, and Y. Cao, "Compact modeling of carbon nanotube transistor for early stage process-design exploration," in Proc. Int. Symp. Low Power Electron. Des., Aug. 2007, pp. 2-7. (Pubitemid 350244530)
9. K. Banerjee, A. Mehrotra, A. Sangiovanni-Vincentelli, and C. Hu, "On thermal effects in deep sub-micron VLSI interconnects," in Proc. Des. Automat. Conf., 1999, pp. 885-891.
10. P. Batude, M. Vinet, A. Pouydebasque, C. L. Royer, B. Previtali, C. Tabone, J.-M. Hartmann, L. Sanchez, L. Baud, V. Carron, A. Toffoli, F. Allain, V. Mazzocchi, D. Lafond, O. Thomas, O. Cueto, N. Bouzaida, D. Fleury, A. Amara, S. Deleonibus, and O. Faynot, "Advances in 3D CMOS sequential integration," in Proc. Int. Electron Devices Meet., Dec. 2009, pp. 1-4.
11. S. Bobba, J. Zhang, A. Pullini, D. Atienza, and G. D. Micheli, "Design of compact imperfection-immune CNFET layouts for standard-cellbased logic synthesis," in Proc. Des., Automat. Test Eur., Apr. 2009, pp. 616-621.
12. S. Bobba, A. Chakraborty, O. Thomas, P. Batude, T. Ernst, O. Faynot, D. Z. Pan, and G. D. Micheli, "CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits," in Proc. Asia South Pacific Des. Automat. Conf., 2011, pp. 337-343.
13. S. Borkar, "Design challenges of technology scaling," IEEE Micro, vol. 19, no. 4, pp. 23-29, Jul.-Aug. 1999.
14. S. Borkar, A. Keshavarzi, J. K. Kurtin, and K. Vivek, "Statistical circuit design with carbon nanotubes," U.S. Patent Applicat. 20070155065, 2005.
15. S. Borkar, "3D integration for energy efficient system design," in Proc. Symp. VLSI Tech., 2009, pp. 58-59.
16. Q. Cao and J. A. Rogers, "Random networks and aligned arrays of single-walled carbon nanotubes for electronic device applications," Nano Res., vol. 1, no. 4, pp. 259-272, 2008.
17. Y. Chai, A. Hazeghi, K. Takei, H.-Y. Chen, P. C. H. Chan, A. Javey, and H.-S. P. Wong, "Low-resistance electrical contact to carbon nanotubes with graphitic interfacial layer," IEEE Trans. Elec. Dev., vol. 59, no. 1, pp. 12-19, Jan. 2012.
18. R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A. Majumdar, M. Metz, and M. Radosavljevic, "Benchmarking nanotechnology for high-performance and low-power logic transistor applications," IEEE Trans. Nanotechnol., vol. 4, no. 2, pp. 153-158, Mar. 2005. (Pubitemid 40421651)
19. Z. Chen, J. Appenzeller, J. Knoch, Y. M. Lin, and P. Avouris, "The role of metal-nanotube contact in the performance of carbon nanotube field-effect transistors," Nano Lett., vol. 5, no. 7, pp. 1497-1502, Jul. 2005. (Pubitemid 41084442)
20. Z. Chen, J. Appenzeller, Y.-M. Lin, J. Sippel-Oakley, A. G. Rinzler, J. Tang, S. J. Wind, P. M. Solomon, and P. Avouris, "An integrated logic circuit assembled on a single carbon nanotube," Science, vol. 311, no. 5768, p. 1735, Mar. 2006.
21. Z. Chen, D. Farmer, S. Xu, R. Gordon, P. Avouris, and J. Appenzeller, "Externally assembled gate-all-around carbon nanotube field-effect transistor," Electron Device Lett., vol. 29, no. 2, pp. 183-185, Feb. 2008. (Pubitemid 351280076)
22. H. Chen et al., "STC: Single-tube characterization methodology for experimental and analytical evaluation of carbon nanotube synthesis," in Proc. Int. Conf. Solid State Devices Mater., 2011, pp. no. C-1-4.
23. G. Close, S. Yasuda, B. Paul, S. Fujita, and H. S. Wong, "A 1 GHz integrated circuit with carbon nanotube interconnects and silicon transistors," Nano Lett., vol. 8, no. 2, pp. 706-709, Feb. 2008. (Pubitemid 351346043)
24. J. P. Colinge, M. H. Gao, A. Romano-Rodriguez, H. Maes, and C. Clae, "Silicon-on-insulator 'gate-all-around device'," in Proc. Int. Electron Devices Meet., 1990, pp. 595-598.
25. P. Collins, S. Arnold, and P. Avouris, "Engineering carbon nanotubes and nanotube circuits using electrical breakdown," Science, vol. 292, no. 5517, pp. 706-709, 2001. (Pubitemid 32385537)
26. J. Cong and Y. Zhang, "Thermal via planning for 3-D IC's," in Proc. Int. Conf. Comput. Aided Des., Nov. 2005, pp. 745-752.
27. J. Cong, G. Luo, J. Wei, and Y. Zhang, "Thermal-aware 3D IC placement via transformation," in Proc. Asia South Pacific Des. Automat. Conf., Jan. 2007, pp. 780-785.
28. D. R. Cox, Renewal Theory. London, U.K.: Methuen & Co., 1962.
29. H. Dai, "Carbon nanotubes: Synthesis, integration, and properties," Acc. Chem. Res., vol. 35, no. 12, pp. 1035-1044, 2002.
30. S. Datta, Electronic Transport in Mesoscopic Systems. Cambridge, U.K.: Cambridge Univ. Press, 1995.
31. A. Davoodi and A. Srivastava, "Variability driven gate sizing for binning yield optimization," IEEE Trans. Very Large Scale Integr. Syst., vol. 16, no. 6, pp. 683-692, Jun. 2008. (Pubitemid 351720887)
32. A. DeHon and H. Naeimi, "Seven strategies for tolerating highly defective fabrication," IEEE Des. Test Comput., vol. 22, no. 4, pp. 306-315, Jul.-Aug. 2005. (Pubitemid 41249776)
33. J. Deng, N. Patil, K. Ryu, A. Badmaev, C. Zhou, S. Mitra, and H.-S. P. Wong, "Carbon nanotube transistor circuits: Circuit-level performance benchmarking and design options for living with imperfections," in Proc. Int. Solid-State Circuits Conf., Feb. 2007, pp. 70-588.
34. J. Deng and H.-S. P. Wong, "A compact SPICE model for carbon nanotube field effect transistors including non-idealities and its applicationpart I: Model of the intrinsic channel region," IEEE Trans. Elec. Dev., vol. 54, no. 12, pp. 3186-3194, Dec. 2007. (Pubitemid 350225926)
35. J. Deng and H. S. P. Wong, "A compact SPICE model for carbonnanotube field-effect transistors including nonidealities and its application-part II: Full device model and circuit performance benchmarking," IEEE Trans. Elec. Dev., vol. 54, no. 12, pp. 3195-3205, Dec. 2007. (Pubitemid 350225927)
36. D. J. Frank, W. Haensch, G. Shahidi, and O. H. Dokumaci, "Optimizing CMOS technology for maximum performance," IBM J. Res. Develop., vol. 50, nos. 4-5, pp. 419-431, 2006. (Pubitemid 44364162)
37. A. D. Franklin, A. Lin, H.-S. P. Wong, and Z. Chen, "Current scaling in aligned carbon nanotube array transistors with local bottom gating," Electron Device Lett., vol. 31, no. 7, pp. 644-646, Jul. 2010.
38. A. D. Franklin, S.-J. Han, G. S. Tulevski, M. Luisier, C. M. Breslin, L. Gignac, M. S. Lundstrom, and W. Haensch, "Sub-10 nm carbon nanotube transistor," in Proc. Int. Electron Devices Meet., 2011, pp. 525-527.
39. S. Fŕegońese, H. C. d'Honincthun, J. Goguet, C. Maneux, T. Zimmer, J.-P. Bourgoin, P. Dollfus, and S. Galdin-Retailleau, "Computationally efficient physics-based compact CNTFET model for circuit design," IEEE Trans. Electron Devices, vol. 55, no. 6, pp. 1317-1327, Jun. 2008. (Pubitemid 351816731)
40. M. S. Fuhrer, J. Nygard, L. Shih, M. Forero, Y.-G. Yoon, M. S. C. Mazzoni, H. J. Choi, J. Ihm, S. G. Louie, A. Zettl, and P. L. McEuen, "Crossed nanotube junctions," Science, vol. 288, no. 5465, pp. 494-497, Apr. 2000. (Pubitemid 30236027)
41. S. C. Goldstein and M. Budiu, "NanoFabrics: Spatial computing using molecular electronics," in Proc. Int. Symp. Comput. Architect., 2001, pp. 178-191.
42. J. Guo, M. Lundstrom, and S. Datta, "Performance projections for ballistic carbon nanotube field-effect transistors," Appl. Phys. Lett., vol. 80, no. 17, pp. 3192-3194, Apr. 2002.
43. J. Guo, A. Javey, H. Dai, and M. Lundstrom, "Performance analysis and design optimization of near ballistic carbon nanotube fieldeffect transistors," in Proc. Int. Electron Devices Meet., Dec. 2004, pp. 703-706. (Pubitemid 40928390)
44. M. R. Guthaus, N. Venkateswarant, C. Visweswariaht, and V. Zolotov, "Gate sizing using incremental parameterized statistical timing analysis," in Proc. Int. Conf. Comput. Aided Des., 2005, pp. 1029-1036.
45. M. Hashimoto, M. Takahashi, and H. Onodera, "Crosstalk noise optimization by post layout transistor sizing," in Proc. Int. Symp. Phys. Des., 2002, pp. 126-130. (Pubitemid 35040034)
46. J. Hone, "Carbon nanotubes: Thermal properties," in Encyclopedia of Nanoscience and Nanotechnology. New York: Marcel Dekker, 2004, pp. 603-610.
47. S. W. Hong, T. Banks, and J. A. Rogers, "Improved density in aligned arrays of single-walled carbon nanotubes by sequential chemical vapor deposition on quartz," Adv. Mater., vol. 22, no. 45, pp. 1826-1830, 2010.
48. M. Horowitz, E. Alon, D. Patil, S. Naffziger, R. Kumar, and K. Bernstein, "Scaling, power, and the future of CMOS," in Proc. Int. Electron. Devices Meet., Dec. 2005, pp. 7-15.
49. C. Huang, Robust Computing with Nano-Scale Devices. New York: Springer, 2010.
50. International Technology Roadmap for Semiconductors. (2009). [Online]. Available: http://public.itrs.net
51. A. Javey, R. Tu, D. B. Farmer, J. Guo, R. G. Gordon, and H. Dai, "High performance nanotube n-FETs with chemically doped contacts," Nano Lett., vol. 5, no. 2, pp. 345-348, 2005.
52. E. Joselevish, H. Dai, J. Liu, K. Hata, and A. H. Windle, "Carbon nanotube synthesis and organization," Top. Appl. Phys., vol. 111, pp. 101-164, 2008.
53. S. J. Kang, C. Kocabas, T. Ozel, M. Shim, N. Pimparkar, M. A. Alam, S. V. Rotkin, and J. A. Rogers, "High-performance electronics using dense, perfectly aligned arrays of single-walled carbon nanotubes," Nat. Nanotechnol., vol. 2, no. 4, pp. 230-236, Apr. 2007. (Pubitemid 46739814)
54. U. Kang, H.-J. Chung, S. Heo, S.-H. Ahn, H. Lee, S.-H. Cha, J. Ahn, D.-M. Kwon, J. H. Kim, J.-W. Lee, H.-S. Joo, W.-S. Kim, H.-K. Kim, E.-M. Lee, S.-R. Kim, K.-H. Ma, D.-H. Jang, N.-S. Kim, M.-S. Choi, S.-J. Oh, J.-B. Lee, T.-K. Jung, J.-H. Yoo, and C. Kim, "8 Gb 3D DDR3 DRAM using through-silicon-via technology," in Proc. Int. Solid-State Circuit Conf., Feb. 2009, pp. 130-131.
55. T. J. Kazmierski, D. Zhou, B. M. Al-Hashimi, and P. Ashburn, "Numerically efficient modeling of CNT transistors with ballistic and nonballistic effects for circuit simulation," IEEE Trans. Nanotechnol., vol. 9, no. 1, pp. 99-107, Jan. 2010.
56. J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, M. J. Interrante, C. S. Patel, R. J. Polastre, K. Sakuma, R. Sirdeshmukh, E. J. Sprogis, S. M. Sri-Jayantha, A. M. Stephens, A. W. Topol, C. K. Tsang, B. C. Webb, and S. L. Wright, "Three-dimensional silicon integration," IBM J. Res. Develop., vol. 52, no. 6, pp. 553-569, Nov. 2008.
57. C. Kocabas, S. J. Kang, T. Ozel, M. Shim, and J. A. Rogers, "Improved synthesis of aligned arrays of single-walled carbon nanotubes and their implementation in thin film type transistors," J. Phys. Chem., vol. 111, no. 48, pp. 17879-17886, 2007. (Pubitemid 350279924)
58. J. Kong, C. Zhou, E. Yenilmez, and H. Dai, "Alkaline metal-doped n-type semiconducting nanotubes as quantum dots," Appl. Phys. Lett., vol. 77, no. 24, pp. 3977-3979, 2000.
59. I. Koren and A. D. Singh, "Fault tolerance in VLSI circuits," Computer, vol. 23, no. 7, pp. 73-83, Jul. 1990. (Pubitemid 20737829)
60. K. J. Kuhn, "Moore's law past 32 nm: Future challenges in device scaling," in Proc. Int. Workshop Comp. Elec., 2009, pp. 1-6.
61. C. Lan, P. Srisungsitthisunti, P. B. Amama, T. S. Fisher, X. Xu, and R. G. Reifenberger, "Measurement of metal/carbon nanotube contact resistance by adjusting contact length using laser ablation," Nanotechnology, vol. 19, no. 12, pp. 1-7, 2008.
62. M. LeMieux, M. C. LeMieux, M. Roberts, S. Barman, Y. W. Jin, J. M. Kim, and Z. Bao, "Self-sorted, aligned nanotube networks for thin-film transistors," Science, vol. 321, no. 5885, pp. 101-104, 2008. (Pubitemid 351956240)
63. Y. Li, D. Mann, M. Rolandi, W. Kim, A. Ural, S. Hung, A. Javey, J. Cao, D. Wang, E. Yenilmez, Q. Wang, J. F. Gibbons, Y. Nishi, and H. Dai, "Preferential growth of semiconducting single-walled carbon nanotubes by a plasma enhanced CVD method," Nano Lett., vol. 4, no. 2, pp. 317-321, 2004. (Pubitemid 38294358)
64. S. K. Lim, "TSV-aware 3D physical design tool needs for faster mainstream acceptance of 3D ICs," in Proc. Des. Automat. Conf. Knowledge Center Article, 2010.
65. M. Lin, A. E. Gamal, Y.-C. Lu, and S. Wong, "Performance benefits of monolithically stacked 3D-FPGA," in Proc. Symp. Field Programmable Gate Arrays, 2006, pp. 113-122. (Pubitemid 44032244)
66. A. Lin, N. Patil, H. Wei, S. Mitra, and H.-S. P. Wong, "ACCNT: A metallic-CNT-tolerant design methodology for carbon-nanotube VLSI: Concepts and experimental demonstration," IEEE Trans. Electron Devices, vol. 56, no. 12, pp. 2969-2978, Dec. 2009.
67. A. Lin, J. Zhang, N. Patil, H. Wei, S. Mitra, and H.-S. P. Wong, "ACCNT: A metallic-CNT-tolerant design methodology for carbonnanotube VLSI: Analyses and design guidelines," IEEE Trans. Electron Devices, vol. 57, no. 9, pp. 2284-2295, Sep. 2010.
68. I. Loi, S. Mitra, T. H. Lee, S. Fujita, and L. Benini, "A low-overhead fault tolerance scheme for TSV-Based 3D network on chip links," in Proc. Int. Conf. Comput. Aided Des., 2008, pp. 598-602.
69. J. Luo, L. Wei, C.-S. Lee, A. Franklin, X. Guan, E. Pop, D. Antoniadis, and H.-S. P. Wong, "Optimization and projection of carbon nanotube field effect transistor performance (CNFET) down to 7 nm gate length including effects of extrinsic resistance and capacitance," in Proc. Int. Electron Devices Meet., in preparation.
70. J. Marulanda and A. Srivastava, "Carrier density and effective mass calculations in carbon nanotubes," Physica Status Solidi (B) Basic Res., vol. 245, no. 11, pp. 2558-2562, Nov. 2008.
71. S. Mitra, J. Zhang, N. Patil, and H. Wei, "Imperfection-immune VLSI logic circuits using carbon nanotube field effect transistors," in Proc. Des., Automat. Test Eur., Apr. 2009, pp. 436-441.
72. E. F. Moore and C. E. Shannon, "Reliable circuits using less reliable relays-part I," J. Franklin Inst., vol. 262, no. 3, pp. 191-208, 1956.
73. N. Moriyama, Y. Ohno, T. Kitamura, S. Kishimoto, and T. Mizutani, "Change in carrier type in high-K gate carbon nanotube field-effect transistors by interface fixed charges," Nanotechnology, vol. 21, no. 16, p. 165201, Apr. 2010.
74. M. Motoyoshi, "Through-silicon via (TSV)," Proc. IEEE, vol. 97, no. 1, pp. 43-48, Jan. 2009.
75. A. Naeemi, R. Sarvari, and J. D. Meindl, "Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI)," Electron Device Lett., vol. 26, no. 2, no. 84-86, 2005. (Pubitemid 40205844)
76. NanGate, Inc. [Online]. Available: http://www.nangate.com
77. S. Natarajan, M. Armstrong, M. Bost, R. Brain, and M. Brazier, "A 32 nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171 μm2 SRAM cell size in a 291Mb array," in Proc. Int. Electron Devices Meet., 2008, pp. 941-943.
78. N. Nemec, D. Toḿanek, and G. Cuniberti, "Modeling extended contacts for nanotube and graphene devices," Phys. Rev. B, vol. 77, no. 12, p. 125420, 2008.
79. K. Nose and T. Sakurai, "Optimization of VDD and VTH for low-power and high-speed applications," in Proc. Asia South Pacific Des. Automat. Conf., 2000, pp. 469-474.
80. (2009). [Online]. Available: http://www.opencores.org
81. (2011). [Online]. Available: http://www.opensparc.net
82. Y. Ouyang, Y. Yoon, J. K. Fodor, and J. Guo, "Comparison of performance limits for carbon nanoribbon and carbon nanotube transistors," Appl. Phys. Lett., vol. 89, no. 20, pp. 1-3, 2006.
83. J.-H. Park, M. Tada, W.-S. Jung, H.-S. P. Wong, and K. C. Saraswat, "Metal-induced dopant (boron and phosphorus) activation process in amorphous germanium for monolithic three-dimensional integration," J. Appl. Phys., vol. 106, no. 7, pp. 1-6, Oct. 2009.
84. N. Patil, J. Deng, H.-S. P. Wong, and S. Mitra, "Automated design of misaligned-carbon-nanotube-immune circuits," in Proc. Des. Automat. Conf., Jun. 2007, pp. 958-961.
85. N. Patil, A. Lin, E. R. Myers, H.-S. P. Wong, and S. Mitra, "Integrated wafer-scale growth and transfer of directional carbon nanotubes and misaligned-carbon-nanotube-immune logic structures," in Proc. Symp. VLSI Tech., Jun. 2008, pp. 205-206.
86. N. Patil, J. Deng, A. Lin, H.-S. P. Wong, and S. Mitra, "Design methods for misaligned and mis-positioned carbon-nanotube-immune circuits," IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., vol. 27, no. 10, pp. 1725-1736, Oct. 2008.
87. N. Patil, J. Deng, S. Mitra, and H.-S. P. Wong, "Circuit-level performance benchmarking and scalability of carbon nanotube transistor circuits," IEEE Trans. Nanotechnol., vol. 8, no. 1, pp. 37-45, Jan. 2009.
88. N. Patil, A. Lin, E. R. Myers, K. Ryu, A. Badmaev, C. Zhou, H.-S. P. Wong, and S. Mitra, "Wafer-scale growth and transfer of aligned single-walled carbon nanotubes," IEEE Trans. Nanotechnol., vol. 8, no. 4, pp. 498-504, Jul. 2009.
89. N. Patil, A. Lin, J. Zhang, H. Wei, K. Anderson, H.-S. P. Wong, and S. Mitra, "VMR: VLSI-Compatible metallic carbon nanotube removal for imperfection-immune cascaded multi-stage digital logic circuits using carbon nanotube FETs," in Proc. Int. Electron. Devices Meet., Dec. 2009, pp. 573-576.
90. N. Patil, A. Lin, J. Zhang, H.-S. P. Wong, and S. Mitra, "Digital VLSI logic technology using carbon nanotube FETs: Frequently asked questions," in Proc. Des. Automat. Conf., Jul. 2009, pp. 304-309.
91. N. Patil, A. Lin, J. Zhang, H. Wei, K. Anderson, H.-S. P. Wong, and S. Mitra, "Scalable carbon nanotube computational and storage circuits immune to metallic and mis-positioned carbon nanotubes," IEEE Trans. Nanotechnol., vol. 10, no. 4, pp. 744-750, Jul. 2011.
92. B. C. Paul, S. Fujita, M. Okajima, and T. Lee, "Modeling and analysis of circuit performance of ballistic CNFET," in Proc. Des. Automat. Conf., 2006, pp. 717-722. (Pubitemid 47113988)
93. B. C. Paul, S. Fujita, M. Okajima, T. H. Lee, H.-S. P. Wong, and Y. Nishi, "Impact of a process variation on nanowire and nanotube device performance," IEEE Trans. Elec. Dev., vol. 54, no. 9, pp. 2369-2376, Sep. 2007. (Pubitemid 351485752)
94. N. Pimparkar, C. Kocabas, S. J. Kang, J. Rogers, and M. A. Alam, "Limits of performance gain of aligned CNT over randomized network: Theoretical predictions and experimental validation," Electron Device Lett., vol. 28, no. 7, pp. 593-595, Jul. 2007. (Pubitemid 47040462)
95. E. Pop, "The role of electrical and thermal contact resistance for Joule breakdown of single-wall carbon nanotubes," Nanotechnology, vol. 19, no. 29, p. 295202, 2008.
96. E. Pop, D. Mann, Q. Wang, K. Goodson, and H. Dai, "Thermal conductance of an individual single-wall carbon nanotube above room temperature," Nano Lett., vol. 6, no. 1, pp. 96-100, 2006. (Pubitemid 43166108)
97. L. Qu, D. Feng, and L. Dai, "Preferential syntheses of semiconducting vertically aligned single-walled carbon nanotubes for direct use in FETs," Nano Lett., vol. 8, no. 9, pp. 2682-2687, 2008.
98. A. Raychowdhury, S. Mukhopadhyay, and K. Roy, "Circuitcompatible modeling of carbon nanotube FETs in the ballistic limit of performance," in Proc. IEEE Conf. Nanotechnol., vol. 2. Aug. 2003, pp. 343-346.
99. A. Raychowdhury, V. K. De, J. Kurtin, S. Y. Borkar, K. Roy, and A. Keshavarzi, "Variation tolerance in a multichannel carbon-nanotube transistor for high-speed digital circuits," IEEE Trans. Elec. Dev., vol. 56, no. 3, pp. 383-392, Mar. 2009.
100. J. A. Rice, Mathematical Statistics and Data Analysis, 2nd ed. Belmont, CA: Duxbury Press, 1994.
101. R. Saito, G. Dresselhaus, and M. Dresselhaus, Physical Properties of Carbon Nanotubes. London, U.K.: Imperial College Press, 1998.
102. S. Sapatnekar, "Addressing thermal and power delivery bottlenecks in 3D circuits," in Proc. Asia South Pacific Des. Automat. Conf., 2009, pp. 423-428.
103. H. Shahidipour, A. Ahmadi, and K. Maharatna, "Effect of variability in SWCNT-based logic gates," in Proc. Int. Symp. Integr. Circuits, 2009, pp. 252-255.
104. M. Shulaker, H. Wei, N. Patil, J. Provine, H. Y. Chen, H. S. Wong, and S. Mitra, "Linear increases in carbon nanotube density through multiple transfer technique," Nano Lett., vol. 11, no. 5, pp. 1881-1886, May 2011.
105. P. M. Solomon, "Contact resistance to a one-dimensional quasiballistic nanotube/wire," Electron Device Lett., vol. 32, no. 3, pp. 246-248, Mar. 2011.
106. A. Sridhar, A. Vincenzi, M. Ruggiero, T. Brunschwiler, and D. Atienza, "3D-ICE: Fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling," in Proc. Int. Conf. Comput. Aided Des., Nov. 2010, pp. 463-470.
107. A. Srivastava, J. M. Marulanda, Y. Xu, and A. K. Sharma, "Current transport modeling of carbon nanotube field effect transistors," Physica Status Solidi (A) Applicat. Mater., vol. 206, no. 7, pp. 1569-1578, Jul. 2009.
108. S. J. Tans, A. R. M. Verschueren, and C. Dekker, "Room-temperature transistor based on a single carbon nanotube," Nature, vol. 393, no. 6680, pp. 49-52, 1998. (Pubitemid 28240249)
109. M. B. Tahoori, "Application-independent defect-tolerance of reconfigurable nano-architectures," ACM J. Emerg. Technol. Comput., vol. 2, no. 3, pp. 197-218, 2006.
110. L. Wei, J. Deng, and H.-S. P. Wong, "Modeling and performance comparison of 1-D and 2-D devices including parasitic gate capacitance and screening effect," IEEE Trans. Nanotechnol., vol. 7, no. 6, pp. 720-727, Nov. 2008.
111. L. Wei, D. J. Frank, L. Chang, and H.-S. P. Wong, "A non-iterative compact model for carbon nanotube FETs incorporating source exhaustion effects," in Proc. Int. Electron Devices Meet., Dec. 2009, pp. 917-920.
112. H. Wei, N. Patil, A. Lin, H.-S. P. Wong, and S. Mitra, "Monolithic three-dimensional integrated circuits using carbon nanotube FETs and interconnects," in Proc. Int. Electron Devices Meet., Dec. 2009, pp. 577-580.
113. H. Wei, N. Patil, J. Zhang, A. Lin, H.-Y. Chen, H.-S. P. Wong, and S. Mitra, "Efficient metallic carbon nanotube removal readily scalable to wafer-level VLSI CNFET circuits," in Proc. Symp. VLSI Tech., Jun. 2010, pp. 237-238.
114. L. Wei, S. Oh, and H.-S. P. Wong, "Performance benchmarks for Si, III-V, TFET, and carbon nanotube FET-re-thinking the technology assessment methodology for complementary logic applications," in Proc. Int. Electron Devices Meet., 2010, pp. 391-394.
115. H. Wei, J. Zhang, L. Wei, N. Patil, A. Lin, M. M. Shulaker, H.-Y. Chen, H.-S. P. Wong, and S. Mitra, "Carbon nanotube imperfectionimmune digital VLSI: Frequently asked questions updated," in Proc. Int. Conf. Comput. Aided Des., Nov. 2011, pp. 227-230.
116. S. Wong, A. El-Gamal, P. Griffin, Y. Nishi, F. Pease, and J. Plummer, "Monolithic 3D integrated circuits," in Proc. VLSI-Technol., Syst. Applicat., Apr. 2007, pp. 1-4.
117. H.-S. P. Wong, S. Mitra, D. Akingwande, C. Beasley, Y. Chai, H.-Y. Chen, X. Chen, G. Close, J. Deng, A. Hazeghi, J. Liang, A. Lin, L. S. Liyanage, J. Luo, J. Parker, N. Patil, M. Shulaker, H. Wei, L. Wei, and J. Zhang, "Carbon nanotube electronics-materials, devices, circuits, design, modeling, and performance projection," in Proc. Int. Electron. Devices Meet., 2011, pp. 501-504.
118. G. Zhang, P. Qi, X. Wang, Y. Lu, X. Li, R. Tu, S. Bangsaruntip, D. Mann, L. Zhang, and H. Dai, "Selective etching of metallic carbon nanotubes by gas-phase reaction," Science, vol. 314, no. 5801, pp. 974-977, Nov. 2006. (Pubitemid 44749938)
119. J. Zhang, N. Patil, A. Hazeghi, and S. Mitra, "Carbon nanotube circuits in the presence of carbon nanotube density variations," in Proc. Des. Automat. Conf., Jul. 2009, pp. 71-76.
120. J. Zhang, N. Patil, and S. Mitra, "Probabilistic analysis and design of metallic-carbon-nanotube-tolerant digital logic circuits," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 28, no. 9, pp. 1307-1320, Sep. 2009.
121. J. Zhang, N. Patil, A. Lin, H.-S. P. Wong, and S. Mitra, "Carbon nanotube circuits: Living with imperfections and variations," in Proc. Des., Automat. Test Eur., Mar. 2010, pp. 1159-1164.
122. J. Zhang, S. Bobba, N. Patil, A. Lin, H.-S. P. Wong, G. D. Micheli, and S. Mitra, "Carbon nanotube correlation: Promising opportunity for CNFET circuit yield enhancement," in Proc. Des. Automat. Conf., Jun. 2010, pp. 889-892.
123. J. Zhang, N. P. Patil, A. Hazeghi, H.-S. P. Wong, and S. Mitra, "Characterization and design of logic circuits in the presence of carbon nanotube density variations," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 30, no. 8, pp. 1103-1113, Aug. 2011.
124. J. Zhang, N. Patil, H.-S. P. Wong, and S. Mitra, "Overcoming carbon nanotube variations through co-optimized technology and circuit design," in Proc. Int. Electron. Devices Meet., Dec. 2011, pp. 87-90.
125. J. Zhang, "Variation-aware design of carbon nanotube digital VLSI circuits," Ph.D. thesis, Dept. Electric. Eng., Stanford Univ., Stanford, CA, 2011.
126. V. Zolotov, D. Blaauw, S. Sirichotiyakul, M. Becer, C. Oh, R. Panda, A. Grinshpon, and R. Levy, "Noise propagation and failure criteria for VLSI designs," in Proc. Int. Conf. Comput.-Aided Des., Nov. 2002, pp. 587-594.