Benchmarking nanotechnology for high-performance and low-power logic transistor applications

IEEE Transactions on Nanotechnology

Volumn 4, Issue 2, 2005, Pages 153-158

  Chau, Robert ^a   Datta, Suman ^a   Doczy, Mark ^a   Doyle, Brian ^a   Jin, Ben ^a   Kavalieros, Jack ^a   Majumdar, Amlan ^a   Metz, Matthew ^a   Radosavljevic, Marko ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Nanotechnology; Semiconductor devices

Indexed keywords

CAPACITANCE; CARBON NANOTUBES; ELECTROSTATICS; LOGIC DEVICES; PERMITTIVITY; SEMICONDUCTING SILICON; TRANSCONDUCTANCE; TRANSISTORS;

INTRINSIC GATE DELAY; LOW POWER LOGIC TRANSISTORS; MOORE'S LAW; NANOELECTRONIC APPLICATIONS;

NANOTECHNOLOGY;

EID: 15844407150     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2004.842073     Document Type: Article

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