A 32nm logic technology featuring 2 nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm 2 SRAM cell size in a 291Mb array

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Natarajan, S ^a   Armstrong, M ^a   Bost, M ^a   Brain, R ^a   Brazier, M ^a   Chang, C H ^a   Chikarmane, V ^a   Childs, M ^a   Deshpande, H ^a   Dev, K ^a   Ding, G ^a   Ghani, T ^a   Golonzka, O ^a   Han, W ^a   He, J ^b   Heussner, R ^a   James, R ^a   Jin, I ^a   Kenyon, C ^a   Klopcic, S ^a   Lee, S H ^a   Liu, M ^a   Lodha, S ^a   McFadden, B ^a   Murthy, A ^a   Neiberg, L ^a   Neirynck, J ^a   Packan, P ^a   Pae, S ^b   Parker, C ^a   Pelto, C ^a   Pipes, L ^a   Sebastian, J ^a   Seiple, J ^a   Sell, B ^a   Sivakumar, S ^a   Song, B ^a   Tone, K ^a   Troeger, T ^a   Weber, C ^c   Yang, M ^a   Yeoh, A ^a   Zhang, K ^a   more..

^a Logic Technology Development   (United States)

^b Quality and Reliability Engineering   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

193NM IMMERSION LITHOGRAPHIES; CELL SIZES; CHANNEL STRAINS; DRIVE CURRENTS; DUAL BANDS; HIGH-K GATE DIELECTRICS; LOGIC TECHNOLOGIES; METAL GATES; PATTERNING LAYERS; PROCESS YIELDS; SRAM CELLS; STRAINED SILICONS; TEST VEHICLES; WORKFUNCTION METALS;

ELECTRON DEVICES; GATES (TRANSISTOR); STATIC RANDOM ACCESS STORAGE;

GATE DIELECTRICS;

EID: 64549151943     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796777     Document Type: Conference Paper

References (3)

1. K. Mistry, et al., IEDM Tech. Dig., p.247, 2007.
2. C. Auth, et al., Symp. VLSI Tech. Dig., p. 128, 2008.
3. D. Ingerly, et al., Intl. Interconnect Tech. Conf., p. 216, 2008.