Through-Silicon Via (TSV)

Proceedings of the IEEE

Volumn 97, Issue 1, 2009, Pages 43-48

  Motoyoshi, Makoto ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Chip size package (CSP); Image sensor; Micro bump; Three dimensional large scale integration (3D LSI); Through silicon via (TSV)

Indexed keywords

ELECTRONICS PACKAGING; IMAGE SENSORS; INTEGRATED CIRCUIT INTERCONNECTS; LSI CIRCUITS; SILICON;

CHIP SIZE PACKAGE; LSI TECHNOLOGY; MASS PRODUCTION; MICRO-BUMPS; PRODUCTION LEVEL; RESEARCH LEVEL; THROUGH-SILICON-VIA (TSV);

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 61549122276     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2008.2007462     Document Type: Article

References (22)

1. M. Bonkohara, in Proc. 6th Annu. KGD Ind. Worfeshop, Session II-3, 1999.
2. M. Koyanagi, "Roadblocks in achieving three-dimensional LSI," in Extended Abst. 8th Symp. Future Electron Devices, 1989, pp. 50-60.
3. H. Takata, T. Nakano, S. Yokoyama, S. Horiuchi, H. Itani, H. Tsukamoto, and M. Koyanagi, "A novel fabrication technology for optically interconnected three-dimensional LSI by wafer aligning and bonding technique," in Extended Abst. 1991 Int. Semiconduct. Device Res. Symp., 1991, pp. 327-330.
4. M. Koyanagi, H. Kurino, T. Matsumoto, K. Sakuma, K. W. Lee, N. Miyakawa, H. Itani, and T. Tsukamoto, "New three dimensional integration technology for future system-on silicon LSIs," in Proc. IEEE Int. Workshop Chip Package Co-Design, 1998, pp. 96-103.
5. M. Koyanagi, H. Kurino, K. W. Lee, K. Sakuma, N. Miyakawa, and H. Itani, "Future system-on-silicon LSI chips," IEEE Micro, vol. 18, no. 4, pp. 17-22, 1998.
6. H. Kurino, K. W. Lee, T. Nakamura, K. Sakuma, H. Hashimoto, K. T. Park, N. Miyakawa, H. Shimazutsu, K. Y. Kim, K. Inamura, and M. Koyanagi, "Intelligent image sensor chip with three dimensional structure," in IEEE IEDM Tech. Dig., 1999, pp. 879-882.
7. K. W. Lee, T. Nakamura, T. Ono, Y. Yamada, T. Mizukusa, H. Hashimoto, K. T. Park, H. Kuřino, and M. Koyanagi, "Three-dimensional shared memory fabricated using wafer stacking technology," in IEEE IEDM Tech. Dig., 2000, pp. 165-168.
8. T. Ono, T. Mizukusa, T. Nakamura, Y. Yamada, Y. Igarashi, T. Morooka, H. Kurino, and M. Koyanagi, "Three-dimensional processor system fabricating by wafer stacking technology," in Proc. Int. Symp. Low-Power High-Speed Chips, 2002, pp. 186-193.
9. M. Motoyoshi, K. Kamibayashi, M. Bonkohara, and M. Koyanagi, "3D-LSI and its key supporting technologies," in Tech. Dig. 3D Architect. Semiconduct. Integr. Packag., Nov. 2006.
10. M. Koyanagi, T. Nakamura, Y. Yamada, H. Kikuchi, T. Fukushima, T. Tanaka, and H. Kurino, "Three-dimensional integration technology based on wafer bonding with vertical buried interconnections," IEEE Trans. Electron Devices, vol. 53, pp. 2799-2808, Nov. 2006.
11. R. H. Dennard, F. H. Gaensslen, V. L. Rideout, E. Bassous, and A. R. LeBlanc, IEEE J. Solid-State Circuits, vol. SC-9, p. 256, 1974.
12. J. Stern and V. Ozguz, "Beyond 3D integration: 3D systems, " in Tech. Dig. Int. 3D Syst. Integr. Conf., 2007, pp. 12.1-12.17.
13. B. Haba, "Wafer-level stacking: Novel approach to stacking very thin die," in Proc. Conf 3-D Architect. Semiconduct. Integr. Packag., Oct. 2007.
14. F. Carson, "Fan-in PoP: Enabling smaller form factor 3D integration, " in Proc. Conf. 3-D Architect. Semiconduct. Integr. Packag., Oct. 2007.
15. M. Robinson, "Bridging the gap to TSV," in Proc. Conf. 3-D Architect. Semiconduct. Integr. Packag., Oct. 2007.
16. A. Fazzi et al., "A 0.14 mAW/Gbps high-density capacitive interface for 3D system integration," in Proc. IEEE CICC, Sep. 2005, pp. 101-104.
17. K. Kanda et al., "A. 1.27 Gb/s/ch 3 mW/pin Wireless Superconnect (WSC) interface scheme," in IEEE ISSCC Dig. Tech. Papers, Feb. 2003, pp. 142-143.
18. M. Bonkohara, M. Motoyoshi, K. Kamibayashi, and M. Koyanagi, "Three dimensional LSI integration technology by 'chip on chip,' 'chip on wafer' and 'wafer on wafer' with system in a package," Proc. Mater. Res. Soc. Symp., vol. 970, pp. 35-45, 2007.
19. M. Motoyoshi, K. Kamibayashi, M. Bonkohara, and M. Koyanagi, "Current and future 3 dimensional LSI technologies," in Tech. Dig. Int. 3D Syst. Integr. Conf, 2007, pp. 8.1-8.14.
20. W. Suntharalingam, R. Berger, J. A. Burns, C Chen, C. Keast, J. M. Knecht, R. D. Lambert, K. L. Newcomb, D. M. O'Mara, D. D. Rathman, D. C. Shaver, A. M. Soares, C. N. Stevenson, B. M. Tyrrell, K. Warner, B. D. Wheeler, W. Yost, and D. J. Young, "Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology," in ISSCC Dig. Tech. Papers, 2005, pp. 356-357.
21. C. Keast, B. Aull, J. Burns, C. Chen, J. Knecht, B. Tyrrell, K. Warner, B. Wheeler, V. Suntharalingam, P. Wyatt, and D. Yost, "Three-dimensional integration technology for advanced focal planes," in Dig. Int. 3D Syst. Integr. Conf., 2007, pp. 3.1-3.16.
22. D. Temple, D. Malta, A. Huffman, M. Lueck, J. E. Robinson, P. R. Coffman, T. B. Welch, M. R. Skokan, A. J. Moll, and W. B. Knowlton, "3-D process technologies for highly integrated microsystems," in Tech. Dig. Int. 3D Syst. Integr. Conf., 2007, pp. 4.1-4.12.