Optimizing CMOS technology for maximum performance

IBM Journal of Research and Development

Volumn 50, Issue 4-5, 2006, Pages 419-431

  Frank, David J ^a   Haensch, Wilfried ^a   Shahidi, Ghavam ^a   Dokumaci, Omer H ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN FOR TESTABILITY; GATES (TRANSISTOR); HEAT LOSSES; MICROPROCESSOR CHIPS; OPTIMIZATION; TRANSISTORS;

HIGH-K GATE INSULATORS; HIGH-MOBILITY SEMICONDUCTORS; METAL GATES;

CMOS INTEGRATED CIRCUITS;

EID: 33748532147     PISSN: 00188646     EISSN: 00188646     Source Type: Journal    
DOI: 10.1147/rd.504.0419     Document Type: Article

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