Performance benefits of monolithically stacked 3D-FPGA

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2006, Pages 113-122

  Lin, Mingjie ^a   Gamal, Abbas El ^a   Lu, Yi Chang ^a   Wong, Simon ^a  

^a Stanford University   (United States)

Author keywords

3D monolithically stacked; FPGA; Performance analysis

Indexed keywords

BLOCK CODES; CMOS INTEGRATED CIRCUITS; CODES (STANDARDS); COMPUTER AIDED LOGIC DESIGN; ENERGY UTILIZATION; MONOLITHIC INTEGRATED CIRCUITS; RANDOM ACCESS STORAGE;

3D MOLITHICALLY STACKED; CMOS LAYERS; PASS-TRANSISTOR SWITCHES; PERFORMANCE ANALYSIS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33745817849     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1117201.1117219     Document Type: Conference Paper

References (23)

1. V. George, Low Energy Field-Programmable Gate Array. PhD thesis, UC Berkeley, 2000.
2. A. DeHon, Reconfigurable Architectures for General-Purpose Computing. PhD thesis, MIT, 1996.
3. E. Kusse and J. Rabaey, "Low-energy embedded FPGA structures," in Proceedings of International Symposium on Low Power Electronics and Design, August 1998.
4. L. Shang, A. S. Kaviani, and K. Bathala, "Dynamic power consumption in Virtex-II FPGA family," in Proceedings of the 2002 ACM/SIGDA Tenth International Symposium on Field-Programmable Gate Arrays, pp. 157-164, 2002.
5. V. Degalahal and T. Tuan, "Methodology for high level estimation of FPGA power consumption," in Proceedings of the Design Automation Conference, pp. 657-660, Jan. 2005.
6. P. S. Zuchowski, C. B. Reynolds, R. J. Grupp, S. G. Davis, B. Cremen, and B. Troxel, "A hybrid ASIC and FPGA architecture," in Proceedings of the 2002 IEEE/ACM International Conference on Computer-Aided Design, pp. 187-194, May 2002.
7. J. Burns, L. McIlrath, J. Hopwood, C. Keast, D. Vu, K. Warner, and P. Wyatt, "An SOI-based three-dimensional integrated circuit technology, " in Proceedings of the SOI Conference, pp. 20-21, Oct. 2000.
8. J. Burns, L. McIlrath, C. Keast, C. Lewis, A. Loomis, K. Warner, and P. Wyatt, "Three-dimensional integrated circuits for low-power, high-bandwidth systems on a chip," in Proceedings of the Solid-State Circuits Conference, pp. 268-269, Feb 2001.
9. A. R. Joshi and K. C. Saraswat, "Nickel induced crystallization of a-Si gate electrode at 500C and MOS capacitor reliability," IEEE Trans. Electron Devices, vol. 50, pp. 1058-1062, April 2003.
10. M. Cao, T. Zhao, K. C. Saraswat, and J. D. Plummer, "A simple EEPROM cell using polysilicon thin film transistors," IEEE Electron Device Letter, vol. 15, pp. 304-306, Aug. 1994.
11. S. Kaeriyama, T. Sakamoto, H. Sunamura, M. Mizuno, H. Kawaura, T. Hasegawa, K. Terabe, T. Nakayama, and M. Aono, "A nonvolatile programmable solid-electrolyte nanometer switch," IEEE J. Solid State Circuits, vol. 40, pp. 168-176, Jan. 2005.
12. A. Rahman, S. Das, A. Chandrakasan, and R. Reif, "Wiring requirement and three-dimensional integration technology for field programmable gate arrays," IEEE Trans. on VLSI Systems, vol. 11, pp. 44-54, Feb. 2003.
13. V. Betz and J. Rose, "VPR: A new packing, placement and routing tool for FPGA research," in Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, pp. 213-222, 1997.
14. Xilinx, Inc., Virtex-II Platform FPGA Handbook, April 2000.
15. G. Lemieux and D. Lewis, "Circuit design of routing switches," in Proceedings of the 2002 ACM/SIGDA Tenth International Symposium on Field-Programmable Gate Arrays, pp. 19-28, 2002.
16. J. Rose, R. Francis, D. Lewis, and P. Chow, "Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency," IEEE Journal of Solid-State Circuits, vol. 25, no. 5, pp. 1217-1225, 1990.
17. E. Ahmed and J. Rose, "The effect of LUT and cluster size on deep-submicron FPGA performance and density," in the 2000 ACM/SIGDA Eighth International Symposium on Field Programmable Gate Arrays, Feb. 2000.
18. V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers, 1999.
19. F. Li, D. Chen, L. He, and J. Cong, "Architecture analysis and automation: Architecture evaluation for power-efficient FPGAs," in Proceedings of the 2003 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, 2003.
20. W. C. Elmore, "The transient analysis of damped linear networks with particular regard to wideband amplifiers," Jour. of Applied Physics, vol. 19, no. 1, pp. 55-63, 1948.
21. N. Nassif, M. Desai, and D. Hall, "Robust Elmore delay models suitable for full chip timing verification of a 600 MHz CMOS microprocessor," in Design Automation Conference, pp. 15-19, Jun. 1998.
22. W. Xu, "VPR for Virtex." Available on: http://www-unix.ecs.umass.edu/~wxu/jbits/VPR_ for_Virtex.htm.
23. S. Yang, "Logic synthesis and optimization benchmarks, version 3.0," tech. rep., Microelectronics Center of North Carolina, 1991.