Gate sizing using incremental parameterized statistical timing analysis

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2005, Issue , 2005, Pages 1029-1036

  Guthaus, M R ^a   Venkateswarant, N ^b   Visweswariah, C ^c   Zolotov, V ^c  

^a The Department of Civil and Environmental Engineering   (United States)

^b IBM   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CORRELATION METHODS; MATHEMATICAL MODELS; OPTIMIZATION; PARAMETER ESTIMATION; PROBABILITY; STATISTICAL METHODS;

CIRCUIT SIMULATIONS; GATE SIZING; STATISTICAL DISTRIBUTIONS; STATISTICAL STATIC TIMING ANALYSIS (SSTA);

DELAY CIRCUITS;

EID: 33751408241     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560213     Document Type: Conference Paper

References (20)

1. A. Agarwal, V. Zolotov, and D. T. Blaauw, "Statistical timing analysis using bounds and selective enumeration," TCAD, vol. 22, no. 9, pp. 1243-1260, September 2003.
2. J. A. G. Jess, K. Kalafala, S. R. Naidu, R. H. J. M. Otten, and C. Visweswariah, "Statistical timing for parametric yield prediction of integrated circuits," in DAC, June 2003, pp. 932-937.
3. C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, and S. Narayan, "First-order incremental block-based statistical timing analysis," in DAC, 2004, pp. 331-336.
4. H. Chang and S. Sapatnekar, "Statistical timing analysis considering spatial correlations using a single PERT-like traversal," in ICCAD, 2003, pp. 621-625.
5. A. Davoodi, V. Khandelwal, and A. Srivastava, "Variability inspired implementation selection problem," in ICCAD, 2004, pp. 423-427.
6. E. T. A. F. Jacobs and M. R. C. M. Berkelaar, "Gate sizing using a statistical delay model," in DATE, March 2000, pp. 283-290.
7. A. Srivastava, D. Sylvester, and D. Blaauw, "Statistical optimization of leakage power considering process variations using dual-Vth and sizing," in DAC, June 2004, pp. 773-779.
8. X. Bai, C. Visweswariah, P. N. Strenski, and D. J. Hathaway, "Uncertainty-aware circuit optimization," in DAC, June 2002, pp. 58-63.
9. M. Mani and M. Orshansky, "A new statistical optimization algorithm for gate sizing," in ICCD, October 2004, pp. 272-277.
10. S. Director, P. Feldmann, and K. Krishnan, "Statistical integrated circuit design," JSSC, vol. 28, no. 3, pp. 193-202, March 1993.
11. I. Sutherland, B. Sproull, and D. Harris, Logical Effort: Designing Fast CMOS Circuits. Morgan Kaufmann Publisher, 1999.
12. J. P. Fishburn and A. E. Dunlop, "TILOS: a posynomial programming approach to transistor sizing," in ICCAD, 1985, pp. 326-328.
13. J. Shyu, A. Sangiovanni-Vincentelli, J. Fishburn, and A. Dunlop, "Optimization-based transistor sizing," JSSC, vol. 23, no. 2, April 1988.
14. S. Sapatnekar, V. Rao, P. Vaidya, and S. Kang, "An exact solution to the transistor sizing problem for cmos circuits using convex optimization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 11, pp. 1621-1632, November 1993.
15. C. E. Clark, "The greatest of a finite set of random variables," in Operations Research, March-April 1961, pp. 145-162.
16. M. Cain, "The moment-generating function of the minimum of bivariate normal random variables," The American Statistician, vol. 48, no. 2, pp. 124-125, May 1994.
17. C. Visweswariah, Dockets YOR9-2003-401 &YOR9-2003-402 & YOR9-2003-403, Filed with the U.S. Patent Office, September 2003.
18. H. Chang, V. Zolotov, S. Narayan, and C. Visweswariah, "Parameterized block-based statistical timing analysis with non-gaussian parameters and non-linear delay functions," in Tau, 2005, pp. 99-104.
19. M. R. Guthaus, N. Venkateswaran, V. Zolotov, D. Sylvester, and R. B. Brown, "Optimization objectives and models of variation for statistical gate sizing," in GLSVLSI, April 2005, pp. 312-316.
20. A. Agarwal, D. Blaauw, and V. Zolotov, "Statistical timing analysis for intra-die process variations with spatial correlations," in ICCAD, 2003, pp. 900-907.