Technologies for ultradynamic voltage scaling

Proceedings of the IEEE

Volumn 98, Issue 2, 2010, Pages 191-214

  Chandrakasan, Anantha P ^a   Daly, Denis C ^a   Finchelstein, Daniel Frederic ^b   Kwong, Joyce ^a   Ramadass, Yogesh Kumar ^a   Sinangil, Mahmut Ersin ^a   Sze, Vivienne ^a   Verma, Naveen ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b NVIDIA   (United States)

Author keywords

Integrated circuits; Low power; Ultradynamic voltage scaling

Indexed keywords

COMPUTATION THEORY; ENERGY EFFICIENCY; ENERGY UTILIZATION; INTEGRATED CIRCUITS; LOGIC DEVICES; STATIC RANDOM ACCESS STORAGE; VOLTAGE SCALING;

BIOMEDICAL MONITORING; BUILDING BLOCKES; H.264/AVC VIDEO; INTEGRATED DC-DC CONVERTERS; LOGIC CELLS; LOW POWER; MOBILE MULTIMEDIA; SUPPLY VOLTAGES;

LOW POWER ELECTRONICS;

EID: 75649145360     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2009.2033621     Document Type: Article

References (97)

1. B. Davari, R. H. Dennard, and G. G. Shahidi, "CMOS scaling for high performance and low-power-the next ten years, "Proc. IEEE, vol.83, no.4, pp. 595-606, Jan. 1996.
2. M. Horowitz, E. Alon, D. Patil, S. Naffziger, R. Kumar, and K. Bernstein, "Scaling, power, and the future of CMOS, "in IEEE Int. Electron Devices Meeting, Dec. 2005, pp. 7-15.
3. K. Itoh, "Adaptive circuits for the 0.5-V nanoscale CMOS era, "in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2009, pp. 14-20.
4. T. D. Burd and R. W. Brodersen, BDesign issues for dynamic voltage scaling, "in Proc. IEEE Int. Symp. Low Power Electronics and Design, Aug. 2000, pp. 9-14.
5. V. Gutnik and A. Chandrakasan, BEmbedded power supply for low-power DSP, "IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 5, no. 4, pp. 425-435, Dec. 1997.
6. Technical Note TN2188 Exporting Movies for iPod, Apple TV and iPhone.
7. [Online]. Available: http://www.developer.apple.com/technotes/tn2007/ tn2188.html
8. BRecommendation ITU-T H.264: Advanced Video Coding for Generic Audiovisual Services, "ITU-T, Tech. Rep., 2003.
9. N10176: Call for Test Materials for Future High-Performance Video Coding Standards Development, ISO/IEC JTC1/SC29/WG11, Oct. 2008.
10. Draft BRequest for Video Test Sequences for Enhanced Performance Video Coding Work[(for Approval), Jul. 2009, VCEG-L93.
11. B. Zhai, L. Nazhandali, J. Olson, A. Reeves, M. Minuth, R. Helfand, S. Pant, D. Blaauw, and T. Austin, BA 2.60 pJ/Inst subthreshold sensor processor for optimal energy efficiency, "in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2006, pp. 154-155.
12. S. Hanson, B. Zhai, M. Seok, B. Cline, K. Zhou, M. Singhal, M. Minuth, J. Olson, L. Nazhandali, T. Austin, D. Sylvester, and D. S. Blaauw, "Performance and variability optimization strategies in a sub-200 mV, 3.5 pJ/inst, 11 nW subthreshold processor, "in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2007, pp. 152-153.
13. tmicrocontroller with integrated SRAM and switched-capacitor dc-dc converter, "in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2008, pp. 318-319.
14. A. C.-W. Wong, D. McDonagh, G. Kathiresan, O. C. Omeni, O. El-Jamaly, T. C.-K. Chan, P. Paddan, and A. J. Burdett, "A 1 V, micropower system-on-chip for vital-sign monitoring in wireless body sensor networks, "in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2008, pp. 138-139.
15. MSP430x4xx Family User's Guide.
16. [Online]. Available: http://www.focus.ti.com/docs/prod/folders/print/ msp430fg4619.html.
17. V. Chan and S. Underwood, A Single-Chip Pulsoximeter Design Using the MSP430.
18. [Online]. Available: http://www.ti.com/litv/pdf/slaa274
19. [Online]. Available: http://www.eplimited.com
20. J. L. Willems, C. Abreu-Lima, P. Arnaud, J. H. van Bemmel, C. Brohet, R. Degani, B. Denis, J. Gehring, I. Graham, and G. van Herpen, "The diagnostic performance of computer programs for the interpretation of electrocardiograms, "New Eng. J. Med., vol.325, no.25, pp. 1767-1773, Dec. 1991.
21. V. Chudacek, M. Huptych, D. Novak, and L. Lhotska, "Automatic QT interval measurement using rule-based gradient method, "in Comput. Cardiol., Sep. 2006, pp. 349-351.
22. D. M. Roden, "Drug-induced prolongation of the QT interval, "New Eng. J. Med., vol.350, no.10, pp. 1013-1022, Mar. 2004.
23. P. M. Okin, R. B. Devereux, ". V. Howard, R. R. Fabsitz, E. T. Lee, and T. K. Welty, "Assessment of QT interval and QT dispersion for prediction of all-cause and cardiovascular mortality in American Indians, "Circulation, vol. 101, pp. 61-66, 2000.
24. B. Calhoun, A. Wang, and A. Chandrakasan, "Modeling and sizing for minimum energy operation in subthreshold circuits, "IEEE J. Solid-State Circuits, vol.40, no.9, pp. 1778-1786, Sep. 2005.
25. P. Macken, M. Degrauwe, M. V. Paemel, and H. Oguey, "A voltage reduction technique for digital systems, "in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1990, pp. 238-239.
26. K. J. Kuhn, "Reducing variation in advanced logic technologies: Approaches to process and design for manufacturability of nanoscale CMOS, "in IEEE Int. Electron Devices Meeting (IEDM), Dec. 2007, pp. 471-474.
27. B. Zhai, S. Hanson, D. Blaauw, and D. Sylvester, "Analysis and mitigation of variability in subthreshold design, "in Proc. IEEE Int. Symp. Low Power Electron. Design, Aug. 2005, pp. 20-25.
28. A. Wang and A. Chandrakasan, BA 180-mV subthreshold FFT processor using a minimum energy design methodology, "IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 310-319, Jan. 2005.
29. J. Chen, L. T. Clark, and Y. Cao, "Robust design of high fan-in/out subthreshold circuits, "in IEEE Int. Conf. Comput. Design: VLSI Comput. Processors, Oct. 2005, pp. 405-410.
30. J. Chen, L. T. Clark, and T.-H. Che, "An ultra-low-power memory with a subthreshold power supply voltage, "IEEE J. Solid-State Circuits, vol.41, no.10, pp. 2344-2353, Oct. 2006.
31. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors, "IEEE J. Solid-State Circuits, vol.24, no.5, pp. 1433-1439, Oct. 1989.
32. t microcontroller with integrated SRAM and switched capacitor dc-dc converter, "IEEE J. Solid-State Circuits, vol.44, no.1, pp. 115-126, Jan. 2009.
33. Y. Cao and L. T. Clark, "Mapping statistical process variations toward circuit performance variability: An analytical modeling approach, "in Proc. ACM IEEE Design Automation Conf., Jun. 2005, pp. 658-663.
34. W. Zhao and Y. Cao, "New generation of predictive technology model for sub-45 nm early design exploration, "IEEE Trans. Electron Devices, vol.53, no.11, pp. 2816-2823, Nov. 2006, verified (IEEE Proc).
35. E. Vittoz and J. Fellrath, "CMOS analog integrated circuits based on weak-inversion operation, "IEEE J. Solid-State Circuits, vol.SC-12, pp. 224-231, Jun. 1977.
36. R. M. Swanson and J. D. Meindl, BIon-implanted complementary MOS transistors in low-voltage circuits, "IEEE J. Solid-State Circuits, vol. SC-7, no. 2, pp. 146-153, Apr. 1972.
37. C. H. Kim, H. Soeleman, and K. Roy, "Ultra-low-power DLMS adaptive filter for hearing aid applications, " IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol.11, no.6, pp. 1058-1067, Dec. 2003.
38. B. Calhoun and A. Chandrakasan, BUltra-dynamic voltage scaling (UDVS) using sub-threshold operation and local voltage dithering in 90 nm CMOS, "in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2005, pp. 300-301.
39. M.-E. Hwang, A. Raychowdhury, K. Kim, and K. Roy, "A 85 mV 40 nW process-tolerant subthreshold 8x8 FIR filter in 130 nm technology, "in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2007, pp. 154-155.
40. V. Sze and A. Chandrakasan, "A 0.4-V UWB baseband processor, "in Proc. IEEE Int. Symp. Low Power Electronics and Design, Aug. 2007, pp. 262-267.
41. A. Raychowdhury, B. Paul, S. Bhunia, and K. Roy, "Computing with subthreshold leakage: Device/circuit/architecture co-design for ultralow-power subthreshold operation, "IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 11, pp. 1213-1224, Nov. 2005.
42. H. Kaul, M. Anders, S. Mathew, S. Hsu, A. Agarwal, R. Krishnamurthy, and S. Borkar, "A 320 mV 56 /iW 411 GOPS/Watt ultra-low voltage motion estimation accelerator in 65 nm CMOS, "in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2008, pp. 316-317.
43. E. Seevinck, F. J. List, and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells, "IEEE J. Solid-State Circuits, vol.SC-22, no.5, pp. 748-754, Oct. 1987.
44. K. Takeda, Y. Hagihara, Y. Aimoto, M. Nomura, Y. Nakazawa, T. Ishii, and H. Kobatake, "A read-static-noise-margin-free SRAM cell for low-Vdd and high-speed applications, "in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2005, pp. 478-479.
45. A. Bhavnagarwala, X. Tang, and J. Meindl, "The impact of intrinsic device fluctuations on CMOS SRAM cell stability, "IEEE J. Solid-State Circuits, vol.36, no.4, pp. 658-665, Apr. 2001.
46. H. Qin, Y. Cao, D. Markovic, A. Vladimirescu, and J. Rabaey, "SRAM leakage suppression by minimizing standby supply voltage, "in Proc. IEEE Int. Symp. Quality Electron. Design, Mar. 2004, pp. 55-60.
47. K. Zhang, U. Bhattachalya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, ". Zheng, and M. Bohr, "A SRAM design on 65 nm cmos technology with integrated leakage reduction scheme, "in Proc. IEEE Symp. VLSI Circuits, Jun. 2004, pp. 294-295.
48. J. Wang and B. Calhoun, "Canary replica feedback for near-DRV standby VDD scaling in a 90 nm SRAM, "in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2007, pp. 29-32.
49. K. Itoh, M. Horiguchi, and T. Kawahara, "Ultra-low voltage nano-scale embedded RAMs, "in Proc. IEEE Int. Symp. Circuits and Syst., May 2006, pp. 245-248. (Pubitemid 46948339)
50. DD and high-speed applications, "IEEE J. Solid-State Circuits, vol.41, no.1, pp. 113-121, Jan. 2006.
51. A. Kawasumi, T. Yabe, Y. Takeyama, O. Hirabayashi, K. Kushida, A. Tohata, T. Sasaki, A. Katayama, G. Fukano, Y. Fujimura, and N. Otsuka, "A single-power-sup ply 0.7 V 1 GHz 45 nm sram with an asymmetrical unit-/3-ratio memory cell, "in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2008, pp. 382-383.
52. L. Chang, D. M. Fried, J. Hergenrother, J. W. Sleight, R. H. Dennard, R. Montoye, L. Sekaric, S. J. McNab, A. W. Topol, C. D. Adams, K. W. Guarini, and W. Haensch, "Stable SRAM cell design for the 32 nm node and beyond, "in Proc. IEEE Symp. VLSI Circuits, Jun. 2005, pp. 128-129.
53. J. P. Kulkarni, K. Kim, and K. Roy, BA 160 mV robust schmitt trigger based subthreshold SRAM, "IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2303-2313, Oct. 2007.
54. B. Calhoun and A. Chandrakasan, "A 256 kb sub-threshold SRAM in 65 nm CMOS, "in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2006, pp. 480-481.
55. T.-H. Kim, J. Liu, J. Kean, and C. H. Kim, "A 0.2 V, 480 kb sunthreshold SRAM with 1 k cells per bitline for ultra-low-voltage computing, "in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2007, pp. 330-331.
56. Z. Liu and V. Kursun, "High read stability and low leakage SRAM cell based on data/bitline decoupling, "in Proc. IEEE Int. Syst. Chip Conf, Sep. 2006, pp. 115-116.
57. I. J. Chang, J.-J. Kim, S. P. Park, and K. Roy, "A 32 kb 10 T subthreshold SRAM array with bit-interleaving and differential read-scheme in 90 nm CMOS, "in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2008, pp. 388-389.
58. t SRAM employing sense-amplifier redundancy, "in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2007, pp. 328-329.
59. K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepath, Y. Wang, ". Zheng, and M. Bohr, "A 3-GHz 70 Mb SRAM in 65 nm cmos technology with integrated column-based dynamic power supply, "in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2005, pp. 474-475.
60. Z. Liu and V. Kursun, "High read stability and low leakage SRAM cell based on data/bitline decoupling, "in Proc. IEEE Int. Syst.-on-Chip Conf., Sep. 2006, pp. 115-116.
61. M. E. Sinangil, N. Verma, and A. P. Chandrakasan, "A reconfigurable 65 nm SRAM achieving voltage scalability from 0.25 v to 1.2 v and performance scalability from 20 khz to 200 MHz, "in Proc. IEEE ESSCIRC, Sep. 2008, pp. 282-285.
62. L. Chang, Y. Nakamura, R. K. Montoye, J. Sawada, A. K. Martin, K. Kinoshita, F. H. Gebara, K. B. Agarwal, D. J. Acharyya, W. Haensch, K. Hosokawa, and D. Jamsek, "A 5.3 GHz 8 T-SRAM with operation down to 0.41 v in 65 nm CMOS, "in Proc. IEEE Symp. VLSI Circuits, Jun. 2007, pp. 252-253.
63. A. Wang and A. Chandrakasan, "A 180-mv subthreshold fft processor using a minimum energy design methodology, "IEEE J. Solid-State Circuits, vol.40, no.1, pp. 310-319, Jan. 2005.
64. Y. Ramadass and A. Chandrakasan, "Minimum energy tracking loop with embedded dc-dc converter delivering voltages down to 250 mv in 65 nm cmos, "in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2007, pp. 64-587.
65. T. Pering, T. Burd, and R. Brodersen, BThe simulation and evaluation of dynamic voltage scaling algorithms, "in Proc. Int. Symp. Low Power Electron. Design, Aug. 1998, pp. 76-81.
66. G.-Y. Wei and M. Horowitz, "A fully digital, energy-efficient, adaptive power-supply regulator, "IEEE J. Solid-State Circuits, vol.34, no.4, pp. 520-528, Apr. 1999.
67. Y. Ramadass and A. Chandrakasan, "Minimum energy tracking loop with embedded dc-dc converter enabling ultra-low-voltage operation down to 250 mv in 65 nm cmos, "IEEE J. Solid-State Circuits, vol.43, no.1, pp. 256-265, Jan. 2008.
68. A. Stratakos, S. Sanders, and R. Brodersen, "A low-voltage cmos dc-dc converter for a portable battery-operated system, "in IEEE Power Electron. Specialists Conf., Jun. 1994, vol.1, pp. 619-626.
69. Y. Ramadass and A. Chandrakasan, "Voltage scalable switched capacitor dc-dc converter for ultra-low-power on-chip applications, "in IEEE Power Electron. Specialists Conf., Jun. 2007, pp. 2353-2359.
70. D. Maksimovic and S. Dhar, BSwitched-capacitor dc-dc converters for low-power on-chip applications, "in IEEE Power Electron. Specialists Conf., Aug. 1999, vol. 1, pp. 54-59.
71. G. Patounakis, Y. Li, and K. Shepard, "A fully integrated on-chip dc-dc conversion and power management system, "IEEE J. Solid-State Circuits, vol.39, no.3, pp. 443-451, Mar. 2004.
72. H. Qin, K. Cao, D. Markovic, A. Vladimirescu, and J. Rabaey. (2005, Jan.). Standby supply voltage minimization for deep sub-micron sram. Microelectron. J. [Online]. pp. 789-800. Available: http://www.gigascale.org/ pubs/822.html
73. B. A. Fette and S. D. DaBell, "Dynamically configurable switched capacitor power supply and method, "U.S. Patent 5 414 614, May 1995.
74. A. Rao, W. McIntyre, U.-K. Moon, and G. Temes, "Noise-shaping techniques applied to switched-capacitor voltage regulators, "IEEE J. Solid-State Circuits, vol.40, no.2, pp. 422-429, Feb. 2005.
75. LM2797/LM2798 120 mA High Efficiency Step-Down Switched Capacitor Voltage Converter With Voltage Monitoring, National Semiconductor Corp.
76. K. Gulati and H.-S. Lee, "A low-power reconfigurable analog-to-digital converter, "IEEE J. Solid-State Circuits, vol.36, no.12, pp. 1900-1911, Dec. 2001.
77. I. Ahmed and D. Johns, "A 50-MS/s (35 mW) to 1-kS/s (15 /iW) power scaleable 10-bit pipelined ADC using rapid power-on opamps and minimal bias current variation, "IEEE J. Solid-State Circuits, vol.40, no.12, pp. 2446-2455, Dec. 2005.
78. N. Verma and A. Chandrakasan, BAn ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes, "IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1196-1205, Dec. 2007.
79. U. Wismar, D. Wisland, and P. Andreani, "A 0.2 V 0.44 /iW 20 kHz analog to digital SA modulator with 57 fJ/conversion FoM, "in Proc. IEEE Eur. Solid State Circuits Conf, Sep. 2006, pp. 187-190.
80. H.-S. Lee and C. Sodini, "Analog-to-digital converters: Digitizing the analog world, "Proc. IEEE, vol.96, no.2, pp. 323-334, Feb. 2008.
81. J. Sauerbrey, D. Schmitt-Landsiedel, and R. Thewes, "A 0.5-V 1-/iW successive approximation ADC, "IEEE J. Solid-State Circuits, vol.38, no.7, pp. 1261-1265, Jul. 2003.
82. B. Murmann, "A/D converter trends: Power dissipation, scaling and digitally assisted architectures, "in Proc. IEEE Custom Integr. Circuits Conf, Sep. 2008, pp. 105-112.
83. D. C. Daly and A. P. Chandrakasan, "A 6-bit, 0.2 V to 0.9 V highly digital flash ADC with comparator redundancy, "in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2008, pp. 554-555.
84. M. Flynn, C. Donovan, and L. Sattler, "Digital calibration incorporating redundancy of flash ADCs, "IEEE Trans. Circuits Syst.-Part II, Analog Digit. Signal Process., vol.50, no.5, pp. 205-213, 2003.
85. D. C. Daly and A. P. Chandrakasan, "A 6-bit, 0.2 V to 0.9 V highly digital flash ADC with comparator redundancy, "IEEE J. Solid-State Circuits, to be published.
86. S. Gambini and J. Rabaey, "Low-power successive approximation converter with 0.5 V supply in 90 nm CMOS, "IEEE J. Solid-State Circuits, vol.42, no.11, pp. 2348-2356, Nov. 2007.
87. A. Wang and A. Chandrakasan, "A 180 mV FFT processor using subthreshold circuit techniques, "in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2004, vol.1, pp. 292-529.
88. V. Sze, D. F. Finchelstein, M. E. Sinangil, and A. P. Chandrakasan, "A 0.7-V 1.8 mW H.264/AVC 720p video decoder, "IEEE J. Solid-State Circuits, vol.44, no.11, Nov. 2009.
89. D. Finchelstein, V. Sze, M. Sinangil, Y. Koken, and A. Chandrakasan, "A low-power 0.7-V H.264 720p video decoder, "in Proc. IEEE Asian Solid State Circuits Conf., Nov. 2008, pp. 173-176.
90. E. Fleming, C.-C. Lin, N. D. Arvind, G. Raghavan, and J. Hicks, "H.264 decoder: A case study in multiple design points, "in Proc. Formal Methods and Models for Co-Design (MEMOCODE), Jun. 2008, pp. 165-174.
91. K. Xu and C.-S. Choy, "A five-stage pipeline, 204 cycles/mb, single-port SRAM-based deblocking filter for H.264/AVC, "IEEE Trans. Circuits Syst. Video Technol., vol.18, no.3, pp. 363-374, Mar. 2008.
92. C.-D. Chien, C.-C. Lin, Y.-H. Shih, H.-C. Chen, C.-J. Huang, C.-Y. Yu, C.-L. Chen, C.-H. Cheng, and J.-I. Guo, "A 252 kgate/71 mW multi-standard multi-channel video decoder for high definition video applications, "in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2007.
93. S. Na, W. Hwangbo, J. Kim, S. Lee, and C.-M. Kyung, "1.8 mW, hybrid-pipelined H.264/AVC decoder for mobile devices, "in Proc. IEEE Asian Solid State Circuits Conf, Nov. 2007.
94. T.-M. Liu, T.-A. Lin, S.-Z. Wang, W.-P. Lee, K.-C. Hou, J.-Y. Yang, and C.-Y. Lee, "A 125 /iW, fully scalable MPEG-2 and H.264/AVC video decoder for mobile applications, "IEEE J. Solid-State Circuits, vol.42, no.1, pp. 161-169, Jan. 2007.
95. C.-C. Lin, J.-W. Chen, H.-C. Chang, Y.-C. Yang, Y.-H. O. Yang, M.-C. Tsai, J.-I. Guo, and J.-S. Wang, "A 160 K Gates/4.5 KB SRAM H.264 video decoder for HDTV applications, "IEEE J. Solid-State Circuits, vol.42, no.1, pp. 170-182, Jan. 2007.
96. D. Ernst, S. Das, S. Lee, D. Blaauw, T. Austin, T. Mudge, N. S. Kim, and K. Flautner. (2004, Nov.). Razor: Circuit-level correction of timing errors for low-power operation. IEEE Micro.
97. [Online]. 24(6) 10-20. Available: http://www.gigascale.org/pubs/590.html