A 160K gates/4.5 KB SRAM H.264 video decoder for HDTV applications

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 1, 2007, Pages 170-181

  Lin, Chien Chang ^b   Chen, Jia Wei ^b   Chang, Hsiu Cheng ^b   Yang, Yao Chang ^b   Yang, Yi Huan Ou ^b   Tsai, Ming Chih ^b   Guo, Jiun In ^b   Wang, Jinn Shyan ^a,b  

^a IEEE

^b NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

Author keywords

H264 AVC video decoder architecture design; Low power consumption; Low cost design

Indexed keywords

H264/AVC VIDEO DECODER ARCHITECTURE DESIGN; LOW COST DESIGN; LOW POWER CONSUMPTION;

COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; COST EFFECTIVENESS; ENERGY DISSIPATION; HIGH DEFINITION TELEVISION; IMAGE CODING; OPTIMIZATION; STATIC RANDOM ACCESS STORAGE;

DECODING;

EID: 33846260132     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.886537     Document Type: Article

References (20)

1. H.264/AVC, ISO/IEC 14496-10, Joint Video Team (JVT) of ISO/IEC MPEG&ITU-T VCEG, 2003.
2. Joint Video Team (JVT) reference software JM9.3.
3. Y. W. Huang, B. Y. Hsieh, T. C. Chen, and L. G. Chen, "Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder," IEEE Trans. Circuits Syst. Video Technol., vol. 15, no. 3, pp. 378-401, Mar. 2005.
4. S. Z. Wang, T. A. Lin, T. M. Liu, and C. Y. Lee, "A new motion compensation design for H.264/AVC decoder," in Proc. IEEE ISCAS, 2005, pp. 4558-4561.
5. Y. Moshe and N. Peleg, "Implementations of H.264/AVC baseline decoder on different digital signal processors," in Proc. 47th Int. Symp. ELMAR, Jun. 2005, pp. 37-40.
6. V. Lappalainen, A. Hallapuro, and T. D. Hamalainen, "Complexity of optimized H.26L video decoder implementation," IEEE Trans. Circuits Syst. Video Technol., vol. 13, no. 7, pp. 717-725, Jul. 2003.
7. X. Zhou, E. Q. Li, and Y. K. Chen, "Implementation of H.264 decoder on general-purpose processors with medio instructions," in Proc. SPIE Conf. Image and Video Communication and Processing, May 2003, pp. 224-235.
8. T. W. Chen, Y. W. Huang, T. C. Chen, Y. H. Chen, C. Y. Tsai, and L. G. Chen, "Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos," in Proc. IEEE ISCAS, 2005, pp. 2931-2934.
9. Y. Hu, A. Simpson, K. McAdoo, and J. Cush, "A high definition H.264/AVC hardware video decoder core for multimedia SoCs," in Proc. IEEE Int. Symp. Consumer Electronics, 2004, pp. 385-389.
10. T. A. Lin, S. Z. Wang, T. M. Liu, and C. Y. Lee, "An H.264/AVC decoder with 4 × 4 block-level pipeline," in Proc. IEEE ISCAS, 2005, pp. 1810-1813.
11. T. M. Liu, T. A. Lin, S. Z. Wang, W. P. Lee, K. C. Hou, J. Y. Yang, and C. Y. Lee, "An 865- μW H.264/AVC video decoder for mobile applications," in Proc. IEEE Asia Solid-State Circuit Conf., Nov. 2005, pp. 301-304.
12. H. Y. Kang, K. A. Jeong, J. Y. Bae, Y. S. Lee, and S. H. Lee, "MPEG4 AVC/H.264 decoder with scalable bus architecture and dual memory controller," in Proc. IEEE ISCAS, 2004, pp. 145-148.
13. H. C. Chang, C. C. Lin, and J. I. Guo, "A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding," in Proc. IEEE ISCAS, 2005, pp. 6110-6113.
14. D. Wu, W. Gao, M. Hu, and Z. Ji, "A VLSI architecture design of CAVLD decoder," in Proc. 5th Int, Conf, ASIC, 2003, pp. 962-995.
15. J. W. Chen, C. R. Chang, and Y. L. Lin, "A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC," in Proc. IEEE ISCAS, 2005, pp. 4525-4528.
16. Y. W. Huang, B. Y. Hsieh, T. C. Chen, and L. G. Chen, "Hardware architecture design for H.264/AVC intra frame coder," in Proc. IEEE ISCAS, 2004, pp. 269-272.
17. Y. W. Huang, T. W. Chen, B. Y. Hsieh, T. C. Wang, T. H. Chang, and L. G. Chen, "Architecture design for deblocking filter in H.264/JVT/AVC," in Proc. IEEE Int. Conf. Multimedia and Expo, 2003, pp. 693-696.
18. Open Verification Library (OVL). [Online]. Available: http://www.eda.org/ovl/
19. MPEG-4/MB-FIE8100 User Guide ver. 1.1. Faraday Technology Corp. [Online]. Available: http://www.faraday-tech.com/index.html
20. C. C. Lin, J. I. Guo, H. C. Chang, Y. C. Yang, J. W. Chen, M. C. Tsai, and J. S. Wang, "A 160kgate 4.5kB SKRAM H.264 video decoder for HDTV applications," in IEEE ISSCC Dig. Tech. Papers, 2006, pp. 1596-1605.