A 3-GHz 70Mb SRAM in 65nm CMOS technology with integrated column-based dynamic power supply

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Zhang, K ^a   Bhattacharya, U ^a   Chen, Z ^a   Hamzaoglu, F ^a   Murray, D ^a   Vallepalli, N ^a   Wang, Y ^a   Zheng, B ^a   Bohr, M ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

POWER CONSUMPTION; POWER SUPPLY; SRAM CHIP; WRITE MARGINS;

ELECTRIC POWER DISTRIBUTION; ENERGY UTILIZATION; MICROPROCESSOR CHIPS; STATIC RANDOM ACCESS STORAGE;

CMOS INTEGRATED CIRCUITS;

EID: 28144454581     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. K. Itoh et al., "A Deep Sub-V, Single Power-Supply SRAM Cell with Multi-Vt, Boosted Storage Node and Dynamic Load," Symp.VLSI Circuits, pp. 132-133, June, 1996.
2. K. Kanda et al., "Two Orders of Magnitude Leakage Power Reduction of Low Voltage SRAM's by Row-by-Row Dynamic Vdd Control (RRDV) Scheme," IEEE Int. ASIC/SOC Conf., pp. 381-385, Sept., 2002.
3. M. Yamaoka, et al., "0.4V Logic-Library-Friendly SRAM Array Using Rectangular-Diffusion Cell and Detla-Boosted-Array Voltage Scheme," IEEE J. Solid-State Circuits, Vol. 39, No. 6, pp. 934-940, June, 2004.
4. 2 SRAM Cell," IEDM Tech. Digest, Dec., 2004.
5. K. Zhang et al., "A SRAM Design on 65nm CMOS Technology with Integrated Leakage Reduction," Symp. VLSI Circuits, pp. 294-295, June, 2004.