SRAM leakage suppression by minimizing standby supply voltage

Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004

Volumn , Issue , 2004, Pages 55-60

  Qin, Huifang ^a   Cao, Yu ^a   Markovic, Dejan ^a   Vladimirescu, Andrei ^a   Rabaey, Jan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; BUFFER STORAGE; COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; ELECTRIC CONDUCTIVITY; ELECTRIC POTENTIAL; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; OPTIMIZATION; STATIC RANDOM ACCESS STORAGE;

DATA PRESERVATION; DATA RETENTION POTENTIAL (DRP); SYSTEM ON CHIP (SOC) DESIGN; VOLTAGE TRANSFER;

LEAKAGE CURRENTS;

EID: 2942687683     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/isqed.2004.1283650     Document Type: Conference Paper

References (8)

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3. S. Kaxiras, Z. Hu, and M. Martonosi, "Cache decay: Exploiting generational behavior to reduce cache leakage power," Proc. of ISCA, pp. 240-251, Jun-Jul 2001.
4. K. Flautner et al, "Drowsy caches: simple techniques for reducing leakage power," Proc. of ISCA, pp. 148-157, May 2002.
5. nd edition, Prentice-Hall 2002.
6. E. Seevinck, F. J. List, and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells", IEEE J. Solid-State Circuits, vol. SC-22, No. 5, pp. 748-754, Oct. 1987.
7. C. Lage et al., "Soft error rate and stored charge requirements in advanced high-density SRAMs," Proc. of IEDM, pp. 821-824, Dec. 1993.
8. K.D.T. Ngo and R. Webster, "Steady-state analysis and design of a switched-capacitor DC-DC converter," Proc. of PESC, pp. 378-385, Jun-Jul 1992.