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Volumn 42, Issue 11, 2007, Pages 2348-2356

Low-power successive approximation converter with 0.5 v supply in 90 nm CMOS

Author keywords

Analog to digital conversion; Charge leakage; CMOS; Digital calibration; Low power; Low voltage; Subthreshold; successive approximation

Indexed keywords

CHARGE LEAKAGE; CMOS; DIGITAL CALIBRATION; LOW POWER; LOW VOLTAGE; SUBTHRESHOLD; SUCCESSIVE APPROXIMATION;

EID: 51549119208     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.906210     Document Type: Conference Paper
Times cited : (58)

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    • G. Van Der Plass et al., "0.16 pJ/conversion-step 2.5 mW 1.25 GS/s 4b ADC in a 90 nm digital CMOS process," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, San Francisco, CA, Feb. 2006, p. 310.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.