-
1
-
-
33947690158
-
A 1.5MS/s 6-bit ADC with 0.5V supply
-
Hangzhou, China, Nov
-
S. Gambini and J. M. Rabaey, "A 1.5MS/s 6-bit ADC with 0.5V supply," in Proc. Asian Solid State Circuits Conf., Hangzhou, China, Nov. 2006, pp. 47-50.
-
(2006)
Proc. Asian Solid State Circuits Conf
, pp. 47-50
-
-
Gambini, S.1
Rabaey, J.M.2
-
3
-
-
0037480686
-
An ultra-low-energy ADC for smart-dust
-
Jul
-
M. D. Scott, B. E. Boser, and K. S. J. Pister, "An ultra-low-energy ADC for smart-dust," IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1123-1129, Jul. 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, Issue.7
, pp. 1123-1129
-
-
Scott, M.D.1
Boser, B.E.2
Pister, K.S.J.3
-
4
-
-
0037246068
-
Low-voltage, low-power voltage reference based on subthreshold MOSFETs
-
Jan
-
G. G. Giustolisi et al., "Low-voltage, low-power voltage reference based on subthreshold MOSFETs," IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 151-154, Jan. 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, Issue.1
, pp. 151-154
-
-
Giustolisi, G.G.1
-
5
-
-
0032675035
-
A CMOS bandgap reference circuit with sub-1V operation
-
May
-
H. Banba et al., "A CMOS bandgap reference circuit with sub-1V operation," IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 670-674, May 1999.
-
(1999)
IEEE J. Solid-State Circuits
, vol.34
, Issue.5
, pp. 670-674
-
-
Banba, H.1
-
6
-
-
70350786259
-
-
Master's thesis, Elect. Eng. Comput. Sci. Dept, Univ. of California, Berkeley
-
D. Gambini, "Design of low voltage analog-to-digital converter in deep-submicron CMOS," Master's thesis, Elect. Eng. Comput. Sci. Dept., Univ. of California, Berkeley, 2007.
-
(2007)
Design of low voltage analog-to-digital converter in deep-submicron CMOS
-
-
Gambini, D.1
-
7
-
-
0037817786
-
A 0.5 V, 1 -W, successive approximation ADC
-
Jul
-
J. Sauerbrey and R. Thewes, "A 0.5 V, 1 -W, successive approximation ADC," IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1261-1265, Jul. 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, Issue.7
, pp. 1261-1265
-
-
Sauerbrey, J.1
Thewes, R.2
-
8
-
-
0001448224
-
A 1 V, 8-bit successive approximation ADC in standard CMOS process
-
Apr
-
S. Mortezapour and E. K. F. Lee, "A 1 V, 8-bit successive approximation ADC in standard CMOS process," IEEE J. Solid-State Circuits, vol. 35, no. 4, pp. 642-646, Apr. 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, Issue.4
, pp. 642-646
-
-
Mortezapour, S.1
Lee, E.K.F.2
-
9
-
-
34547154701
-
0.16 pJ/conversion-step 2.5 mW 1.25 GS/s 4b ADC in a 90 nm digital CMOS process
-
San Francisco, CA, Feb
-
G. Van Der Plass et al., "0.16 pJ/conversion-step 2.5 mW 1.25 GS/s 4b ADC in a 90 nm digital CMOS process," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, San Francisco, CA, Feb. 2006, p. 310.
-
(2006)
IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers
, pp. 310
-
-
Van Der Plass, G.1
-
10
-
-
33947364789
-
An analysis of latch comparator offset due to load capacitor mismatch
-
Dec
-
A. Nikoozadeh and B. Murmann, "An analysis of latch comparator offset due to load capacitor mismatch," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 12, pp. 1398-1402, Dec. 2006.
-
(2006)
IEEE Trans. Circuits Syst. II, Exp. Briefs
, vol.53
, Issue.12
, pp. 1398-1402
-
-
Nikoozadeh, A.1
Murmann, B.2
|