메뉴 건너뛰기




Volumn , Issue , 2009, Pages 14-20

Adaptive circuits for the 0.5-V nanoscale CMOS era

Author keywords

[No Author keywords available]

Indexed keywords


EID: 70349292880     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977291     Document Type: Conference Paper
Times cited : (59)

References (45)
  • 1
    • 44849138475 scopus 로고    scopus 로고
    • Low-voltage limitations of memory-rich nano-scale CMOS LSIs
    • Sept.
    • K. Itoh, et al., "Low-voltage limitations of memory-rich nano-scale CMOS LSIs," ESSCIRC Dig., pp. 68-75, Sept. 2007.
    • (2007) ESSCIRC Dig. , pp. 68-75
    • Itoh, K.1
  • 2
    • 70349282226 scopus 로고    scopus 로고
    • Low-Voltage Scaling Limitations for Nano-Scale CMOS LSIs
    • to be published in
    • K. Itoh and M. Horiguchi, "Low-Voltage Scaling Limitations for Nano-Scale CMOS LSIs," Solid-State Electronics, to be published in 2008.
    • (2008) Solid-State Electronics
    • Itoh, K.1    Horiguchi, M.2
  • 5
    • 0346267670 scopus 로고    scopus 로고
    • Review and prospects of low-voltage RAM circuits
    • Sep./Nov.
    • Y. Nakagome, et al., "Review and prospects of low-voltage RAM circuits," IBM J. R & D, vol. 47, no. 5/6, pp. 525-552, Sep./Nov. 2003.
    • (2003) BM J. R & D , vol.47 , Issue.5-6 , pp. 525-552
    • Nakagome, Y.1
  • 6
    • 2442653656 scopus 로고    scopus 로고
    • Interconnect limits on Gigascale Integration (GSI) in the 21st century
    • March
    • J. A. Davis, et al., "Interconnect Limits on Gigascale Integration (GSI) in the 21st Century," Proc. of the IEEE, vol.89, no.3, pp.305-324, March 2001.
    • (2001) Proc. of the IEEE , vol.89 , Issue.3 , pp. 305-324
    • Davis, J.A.1
  • 7
    • 2442653656 scopus 로고    scopus 로고
    • Interconnect limits on Gigascale Integration (GSI) in the 21st century
    • March
    • W. Haensch, et al., " Silicon CMOS devices beyond scaling," IBM J. Res. Dev., vol. 50, no. 4/5, pp. 339-361, July/Sept. 2006.
    • (2001) Proc. of the IEEE , vol.89 , Issue.3 , pp. 305-324
    • Davis, J.A.1
  • 8
    • 39749162082 scopus 로고    scopus 로고
    • Where CMOS is going: Trendy hype vs. real technology
    • Feb.
    • T.C. Chen, "Where CMOS is going: Trendy Hype vs. Real Technology," ISSS Dig. Tech. Papers, pp.22-28, Feb. 2006.
    • (2006) ISSS Dig. Tech. Papers , pp. 22-28
    • Chen, T.C.1
  • 9
    • 33748533457 scopus 로고    scopus 로고
    • Three-dimensional integrated circuits
    • July/Sept.
    • A.W. Topol, et al., "Three-dimensional integrated circuits," IBM J. Res. Dev., vol. 50, no. 4/5, pp. 491-506, July/Sept. 2006.
    • (2006) IBM J. Res. Dev. , vol.50 , Issue.4-5 , pp. 491-506
    • Topol, A.W.1
  • 10
    • 0024754187 scopus 로고
    • Matching properties of MOS transistors
    • M.J.M Pelgrom, et al., "Matching properties of MOS transistors," J. SSC Oct. 1989; 24(5):1433-1439.
    • (1989) J. SSC Oct. , vol.24 , Issue.5 , pp. 1433-1439
    • Pelgrom, M.J.M.1
  • 11
    • 48649087666 scopus 로고    scopus 로고
    • Understanding random threshold voltage fluctuation by comparing multiple fabs and technologies
    • Dec.
    • K. Takeuchi, et al., "Understanding Random Threshold Voltage Fluctuation by Comparing Multiple Fabs and Technologies," IEDM Dig. pp. 467-470, Dec. 2007.
    • (2007) IEDM Dig. , pp. 467-470
    • Takeuchi, K.1
  • 12
    • 54949151196 scopus 로고    scopus 로고
    • Approach for physical design in sub-100 nm era
    • May
    • H. Masuda, et al., "Approach for physical design in sub-100 nm era," ISCAS pp. 5934-5937(6), May 2005.
    • (2005) ISCAS , vol.6 , pp. 5934-5937
    • Masuda, H.1
  • 13
    • 34548835200 scopus 로고    scopus 로고
    • Statistical characterization and on-chip measurement methods for local random variability of a process using sense-amplifier-based test structure
    • Feb.
    • S. Mukhopadhyay, et al., "Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test Structure," ISSCC Dig., pp. 400-401, Feb. 2007.
    • (2007) ISSCC Dig. , pp. 400-401
    • Mukhopadhyay, S.1
  • 14
    • 33645652998 scopus 로고    scopus 로고
    • A self-tuning DVS processor using delay-error detection and correction
    • S. Das, et al., "A self-tuning DVS processor using delay-error detection and correction," J. SSC April 2006; 41(4): 792-804.
    • J. SSC April 2006 , vol.41 , Issue.4 , pp. 792-804
    • Das, S.1
  • 15
    • 34548864074 scopus 로고    scopus 로고
    • Fine-grain redundant logic using defect-prediction flip-flops
    • Feb.
    • T. Nakura, et al., "Fine-Grain Redundant Logic Using Defect-Prediction Flip- Flops," ISSCC Dig., pp. 402-403, Feb. 2007.
    • (2007) ISSCC Dig. , pp. 402-403
    • Nakura, T.1
  • 16
    • 49549105128 scopus 로고    scopus 로고
    • In situ error detection and correction for PVT and SER tolerance
    • Feb.
    • D. Blaauw, et al., "In Situ Error Detection and Correction for PVT and SER Tolerance," ISSCC Dig., pp. 400-401, Feb. 2008.
    • (2008) ISSCC Dig. , pp. 400-401
    • Blaauw, D.1
  • 17
    • 0029702076 scopus 로고    scopus 로고
    • A deep sub-V, single power-supply SRAM cell with multi-VT, boosted storage node and dynamic load
    • June
    • K. Itoh, et al., "A deep sub-V, single power-supply SRAM cell with multi-VT, boosted storage node and dynamic load," Symp. VLSI Circuits Dig., pp. 132-133, June 1996.
    • (1996) Symp. VLSI Circuits Dig. , pp. 132-133
    • Itoh, K.1
  • 18
    • 34548845553 scopus 로고    scopus 로고
    • Implementation of the CELL broadband engine in a 65nm SOI technology featuring dual-supply SRAM arrays supporting 6GHz at 1.3V
    • Feb.
    • J. Pille, et al., "Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V," ISSCC Dig., pp. 322-323, 606, Feb. 2007.
    • (2007) ISSCC Dig. , vol.606 , pp. 322-323
    • Pille, J.1
  • 20
    • 2442719367 scopus 로고    scopus 로고
    • A 300MHz 25mA/Mb leakage On-Chip SRAM Module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor
    • Feb.
    • M. Yamaoka, et al., "A 300MHz 25mA/Mb Leakage On-Chip SRAM Module Featuring Process-Variation Immunity and Low-Leakage-Active Mode for Mobile- Phone Application Processor," ISSCC Dig. Tech. Papers, pp. 494-495, Feb. 2004.
    • (2004) ISSCC Dig. Tech. Papers , pp. 494-495
    • Yamaoka, M.1
  • 22
    • 34548822802 scopus 로고    scopus 로고
    • A 4.2GHz 0.3mm2 256kb dual-Vcc SRAM building block in 65nm CMOS
    • Feb.
    • M. Khellah, et al., "A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS," ISSCC Dig., pp.624-625, Feb. 2006.
    • (2006) ISSCC Dig. , pp. 624-625
    • Khellah, M.1
  • 23
    • 49549092261 scopus 로고    scopus 로고
    • A 153Mb-SRAM design with dynamic stability enhancement and leakage reduction in 45nm High-ê metal-gate CMOS technology
    • Feb.
    • F. Hamzaoglu, et al., "A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-ê Metal-Gate CMOS Technology," ISSCC Dig., pp. 376-377, Feb. 2008.
    • (2008) ISSCC Dig. , pp. 376-377
    • Hamzaoglu, F.1
  • 24
    • 49549091784 scopus 로고    scopus 로고
    • A 450ps access-time SRAM macro in 45nm SOI featuring a two-stage sensing scheme and dynamic power management
    • Feb.
    • H. Pilo, et al., "A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two- Stage Sensing Scheme and Dynamic Power Management," ISSCC Dig., pp. 378-379, Feb. 2008.
    • (2008) ISSCC Dig. , pp. 378-379
    • Pilo, H.1
  • 25
    • 25844527781 scopus 로고    scopus 로고
    • Low-power embedded SRAM modules with expanded margins for writing
    • Feb.
    • M. Yamaoka, et al., "Low-power embedded SRAM modules with expanded margins for writing," ISSCC Dig., pp. 480-481, Feb. 2005.
    • (2005) ISSCC Dig. , pp. 480-481
    • Yamaoka, M.1
  • 26
    • 28144454581 scopus 로고    scopus 로고
    • A 3-GHz 70MB SRAM in 65nm CMOS technology with integrated column-based dynamic power supply
    • Feb
    • K. Zhang, et al., "A 3-GHz 70MB SRAM in 65nm CMOS technology with integrated column-based dynamic power supply," ISSCC Dig., pp. 474-475, 611, Feb. 2005.
    • (2005) ISSCC Dig. , vol.611 , pp. 474-475
    • Zhang, K.1
  • 27
    • 58049102639 scopus 로고    scopus 로고
    • A cell-activation-time controlled SRAM for low-voltage operation in DVFS SoCs using dynamic stability analysis
    • Sept.
    • M. Yamaoka, et al., "A Cell-activation-time Controlled SRAM for Low-voltage Operation in DVFS SoCs Using Dynamic Stability Analysis," ESSCIRC Dig., pp. 286- 289, Sept. 2008.
    • (2008) ESSCIRC Dig. , pp. 286-289
    • Yamaoka, M.1
  • 28
    • 37749013850 scopus 로고    scopus 로고
    • A 5.3GHz 8T-SRAM with operation down to 0.41V in 65nm CMOS
    • L. Chang, et al., "A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS," Symp. VLSI Circuits Dig., pp. 252-253, 2007.
    • (2007) Symp. VLSI Circuits Dig. , pp. 252-253
    • Chang, L.1
  • 29
    • 41549168299 scopus 로고    scopus 로고
    • Reducing variation in advanced logic technologies: Approaches to Process and design for manufacturability of nanoscale CMOS
    • Dec.
    • K.J. Kuhn, "Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS," IEDM Dig. pp. 471- 474, Dec. 2007.
    • (2007) IEDM Dig. , pp. 471-474
    • Kuhn, K.J.1
  • 30
    • 51949102860 scopus 로고    scopus 로고
    • Smallest Vth variability achieved by intrinsic thin channel on thin box (SOTB) CMOS with single metal gate
    • June
    • Y. Morita, et al., "Smallest Vth Variability Achieved by Intrinsic Thin Channel on Thin BOX (SOTB) CMOS with Single Metal Gate," Symp. VLSI Tech. Dig., pp.166-167, June 2008.
    • (2008) Symp. VLSI Tech. Dig. , pp. 166-167
    • Morita, Y.1
  • 31
    • 0024918341 scopus 로고
    • A fully Depleted Lean-Channel Transistor (DELTA)-A novel vertical ultra thin SOI MOSFET
    • D. Hisamoto, et al., "A Fully Depleted Lean-Channel Transistor (DELTA)-A Novel Vertical Ultra Thin SOI MOSFET," IEDM Dig., pp. 833-836, 1989.
    • (1989) IEDM Dig. , pp. 833-836
    • Hisamoto, D.1
  • 32
    • 41149171855 scopus 로고    scopus 로고
    • Tri-gate trnsistor architecture with high-ê gate dielectrics, metal gates and strain engineering
    • June
    • J. Kavalieros et al., "Tri-Gate Trnsistor Architecture with High-ê Gate Dielectrics, Metal Gates and Strain Engineering," Symp. VLSI Tech. Dig., pp. 62-63, June 2006.
    • (2006) Symp. VLSI Tech. Dig. , pp. 62-63
    • Kavalieros, J.1
  • 33
    • 60649096765 scopus 로고    scopus 로고
    • The role of the trench capacitor in DRAM innovation
    • Jan.
    • H. Sunami, "The role of the Trench Capacitor in DRAM Innovation," IEEE SSCS News, Winter 2008, pp. 42-44, Jan. 22, 2008.
    • (2008) IEEE SSCS News, Winter 2008 , vol.22 , pp. 42-44
    • Sunami, H.1
  • 34
    • 21644481387 scopus 로고    scopus 로고
    • A highly manufacturable deep trench based DRAM cell layout with a planar array device in a 70nm technology
    • Dec.
    • J. Amon, et al., "A highly manufacturable deep trench based DRAM cell layout with a planar array device in a 70nm technology," IEDM Dig. pp.73-76, Dec. 2004.
    • (2004) IEDM Dig. , pp. 73-76
    • Amon, J.1
  • 35
    • 0347346114 scopus 로고
    • Sub-1-V swing bus architecture for future low-power ULSIs
    • June
    • Y. Nakagome et al., "Sub-1-V swing bus architecture for future low-power ULSIs", Symp. VLSI Circuits Dig., pp. 82-83, June 1992.
    • (1992) Symp. VLSI Circuits Dig. , pp. 82-83
    • Nakagome, Y.1
  • 36
    • 34748842263 scopus 로고    scopus 로고
    • Low-voltage limitations of deep-sub-100-nm CMOS LSIs: View of memory designers
    • DOI 10.1145/1228784.1228789, 1228789, GLSVLSI'07: Proceedings of the 2007 ACM Great Lakes Symposium on VLSI
    • K. Itoh et al., "Low-Voltage Limitations of Deep-Sub-100-nm CMOS LSIs-View of Memory Designers-," GLSVLSI2007, Proc., pp. 529-533, March 2007. (Pubitemid 47469794)
    • (2007) Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI , pp. 529-533
    • Itoh, K.1    Yamaoka, M.2    Kawahara, T.3
  • 37
    • 0026257568 scopus 로고
    • A 2-ns Cycle, 3.8-ns access 512Kb CMOS ECL SRAM with a fully pipelined architecture
    • Nov.
    • T. Chappel, et al., "A 2-ns Cycle, 3.8-ns Access 512Kb CMOS ECL SRAM with a Fully Pipelined Architecture," IEEE JSSC, pp. 1577-1584, Nov. 1991.
    • (1991) IEEE JSSC , pp. 1577-1584
    • Chappel, T.1
  • 38
    • 0031651840 scopus 로고    scopus 로고
    • A 1V 0.9mW at 100MHz 2x16b SRAM utilizing a half-swing pulsed-decoder and write-bus architecture in 0.25μ m dual-Vt CMOS
    • Feb.
    • T. Mori, et al., "A 1V 0.9mW at 100MHz 2x16b SRAM utilizing a Half-Swing Pulsed-Decoder and Write-Bus Architecture in 0.25μ m Dual-Vt CMOS," ISSCC Dig., pp. 354-355, Feb. 1998.
    • (1998) ISSCC Dig. , pp. 354-355
    • Mori, T.1
  • 39
    • 0003605103 scopus 로고    scopus 로고
    • A 940MHz data-rate 8Mb CMOS SRAM
    • Feb.
    • G. Braceras, et al., "A 940MHz Data-Rate 8Mb CMOS SRAM," ISSCC Dig., pp. 198-199, Feb. 1999.
    • (1999) ISSCC Dig. , pp. 198-199
    • Braceras, G.1
  • 40
    • 0001496647 scopus 로고    scopus 로고
    • A 390mm2 16 Bank 1Gb DDR SDRAM with hybrid bitline architecture
    • Feb.
    • T. Kirihata, et al., "A 390mm2 16 Bank 1Gb DDR SDRAM with Hybrid Bitline Architecture," ISSCC Dig. pp. 422-423, Feb. 1999.
    • (1999) ISSCC Dig. , pp. 422-423
    • Kirihata, T.1
  • 41
    • 51949114723 scopus 로고    scopus 로고
    • A 167-processor 65 nm computational platform with per-processor dynamic supply voltage and dynamic clock frequency scaling
    • June
    • D. Truong, et al., "A 167-processor 65 nm Computational Platform with Per- Processor Dynamic Supply Voltage and Dynamic Clock Frequency Scaling," Symp. VLSI Circuits Dig., pp. 22-23, June 2008.
    • (2008) Symp. VLSI Circuits Dig. , pp. 22-23
    • Truong, D.1
  • 42
    • 64549083627 scopus 로고    scopus 로고
    • Comprehensive Study on Vth Variability in Silicon on Thin BOX(SOTB) CMOS with small random-dopant fluctuation: Finding a way to further reduce variation
    • 10.5, Dec.
    • N. Sugii et al., "Comprehensive Study on Vth Variability in Silicon on Thin BOX(SOTB) CMOS with Small Random-Dopant Fluctuation: Finding a Way to Further Reduce Variation," IEDM Dig., 10.5, Dec. 2008.
    • (2008) IEDM Dig.
    • Sugii, N.1
  • 43
    • 64549133760 scopus 로고    scopus 로고
    • High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding
    • 10.4, Dec.
    • O. Weber, et al., "High Immunity to Threshold Voltage Variability in Undoped Ultra-Thin FDSOI MOSFETs and its Physical Understanding," IEDM Dig., 10.4, Dec. 2008.
    • (2008) IEDM Dig.
    • Weber, O.1
  • 44
    • 70349291222 scopus 로고    scopus 로고
    • Low-VT small-offset gated preamplifier for Sub-1-V gigabit DRAM arrays
    • Feb.
    • S. Akiyama et al., "Low-VT Small-offset Gated Preamplifier for Sub-1-V Gigabit DRAM Arrays," ISSCC Dig., Feb. 2009.
    • (2009) ISSCC Dig.
    • Akiyama, S.1
  • 45
    • 34548858682 scopus 로고    scopus 로고
    • An 80-Tile 1.28TFLOPS network-on-chip in 65nm CMOS
    • Feb.
    • S. Vanbal et al., "An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS," ISSCC Dig., pp.98-99, Feb. 2007.
    • (2007) ISSCC Dig. , pp. 98-99
    • Vanbal, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.