Reducing variation in advanced logic technologies: Approaches to process and design for manufacturability of nanoscale CMOS

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2007, Pages 471-474

  Kuhn, Kelin J ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON DEVICES; MACHINE DESIGN; PROCESS DESIGN;

DESIGN FOR MANUFACTURABILITY; MITIGATION STRATEGIES; NANO-SCALE CMOS; PROCESS VARIATIONS; RING OSCILLATORS; TEST METHODS; WITHIN-DIE;

PROCESS ENGINEERING;

EID: 41549168299     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2007.4418976     Document Type: Conference Paper

References (22)

1. S. Borkar, "Designing reliable systems from unreliable components: the challenges of transistor variability and degradation," IEEE Micro, 26:6, pp. 10-16, Nov-Dec. 2005.
2. S. Springer et al., "Modeling of Variation in Submicrometer CMOS ULSI Technologies," IEEE Trans. on Elec. Dev., 53:9, pp. 2168-78, Sept. 2006,
3. H. Mahmoodi, S. Mukhopadhyay and K. Roy, "Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits," IEEE J. of Solid State Circuits, 40:9, pp 1787-1795, Sept. 2005.
4. H.Fukutome et al., "Direct Evaluation of Gate Line Edge Roughness Impact on Extension Profiles in Sub-50-nm n-MOSFETs," IEEE Trans. Elec. Dev., 53:11, pp 2755-2763, Nov. 2006.
5. M. Miyamura, "SRAM critical yield evaluation based on comprehensive physical/statistical modeling, considering anomalous non-Gaussian intrinsic transistor fluctuations," 2007 Sym. VLSI Tech., pp. 22-23.
6. A. Asenov, S. Kaya, and J.H. Davies, "Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variations," IEEE Trans. on Elec. Dev., 49:1, pp. 112-119, Jan. 2002,
7. J. R. Brews, "Surface potential fluctuations generated by interface charge inhomogeneities in MOS devices," J. Appl. Phys., vol. 43, pp. 2306-2313, 1972
8. L. Capodieci, "From optical proximity correction to lithography-driven physical design (1996-2006): 10 years of resolution enhancement technology and the roadmap enablers for the next decade," Proc. SPIE Vol. 6154, 615401
9. C.T. Liu et al., " Severe thickness variation of sub-3nm gate oxide due to Si surface faceting, poly-Si intrusion and corner stress" 006 Sym. VLSI Tech., pg. 75
10. T.K. Yu, et al., "A two-dimensional low pass filter model for die-level topography variation resulting from chemical mechanical polishing of ILD films," IEDM 1999, pp 909-912.
11. I. Ahsan et al., "RTA-Driven Intra-Die Variations in Stage Delay, and Parametric Sensitivities for 65nm Technology," 2006 Sym. VLSI Tech. pp. 170-1
12. T. Tanaka et al., "Vth fluctuation induced by statistical variation of pocket dopant profile," IEDM 2006, pp 271-274
13. A. Asenov, "Simulation of Statistical Variability in Nano MOSFETs," 2007 Sym. VLSI Tech., pg. 86-7
14. E. Fetzer, "Using Adaptive Circuits to Mitigate Process Variations in a Microprocessor Design," IEEE Design.and Test of Computers, 23:6, pp. 476-483, June 2006.
15. P. Stolk, F. Widdershoven, and D/ Klaassen, "Modeling statistical dopant fluctuations in MOS transistors" IEEE Trans. on Elec. Dev., 45:9, pp 1960-1971, Sept. 1998.
16. A. Asenov, Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFET's: A 3-D "atomistic" simulation study ," IEEE Trans. on Elec. Dev., 45:12, pp. 2505-2513, Dec. 1998.
17. H. Yang, et. al, "Current mismatch due to local dopant fluctuations in MOSFET channel," IEEE Trans. on Elec. Dev., 50:11, pp. 2248-2254, Nov. 2003.
18. J. Kavalieros et. al, "Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering, 2006 Sym. VLSI Tech., pg. 50-1.
19. K. Zhang et al., "SRAM design on 65nm CMOS technology with integrated leakage reduction scheme," 2004 Sym. VLSI Cir., pp. 294-5.
20. S. Bhunia, S. Mukhopadhyay, and K. Roy, "Process Variations and Process-Tolerant Design," Int'l Conf. on VLSI Design, 2007, pp. 699-704 and similar.
21. K Soumyanath, S. Borkar, Z. Chunyan and B. Bloechel, "Accurate on-chip interconnect evaluation: a time-domain technique," IEEE J. of SS Cir., pp. 623-631, May 1999.
22. V. Mehrotra, "Modeling the effects of manufacturing variation on high-speed microprocessor interconnect performance," IEDM 1998, pp767-770.