A 180-mV subthreshold FFT processor using a minimum energy design methodology

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 1, 2005, Pages 310-319

  Wang, Alice ^a   Chandrakasan, Anantha ^b  

^a TEXAS INSTRUMENTS   (United States)

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

CMOS digital integrated circuits; CMOS memory circuits; Coprocessors; Design methodology; Digital signal processors; Leakage currents; Logic design; Subthreshold CMOS circuits

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; DIGITAL SIGNAL PROCESSING; FAST FOURIER TRANSFORMS; LEAKAGE CURRENTS; LOGIC DESIGN; MICROSENSORS; PROGRAM PROCESSORS; WIRELESS TELECOMMUNICATION SYSTEMS;

CMOS DIGITAL INTEGRATED CIRCUITS; CMOS MEMORY CIRCUITS; COPROCESSORS; DESIGN METHODOLOGY; DIGITAL SIGNAL PROCESSORS; SUBTHRESHOLD CMOS CIRCUITS;

DIGITAL CIRCUITS;

EID: 11944273157     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.837945     Document Type: Conference Paper

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