A 252kgate/71mW multi-standard multi-channel video decoder for high definition video applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 282-284

  Chien, Chih Da ^a   Lin, Chien Chang ^a   Shih, Yi Hung ^a   Chen, He Chun ^a   Huang, Chia Jui ^a   Yu, Cheng Yen ^a   Chen, Chin Liang ^b   Cheng, Ching Hwa ^b   Guo, Jiun In ^a  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

^b FENG CHIA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

DECODING; ELECTRIC POWER UTILIZATION; IMAGE COMPRESSION; REAL TIME SYSTEMS;

H.264 DECODING; INTERNAL MEMORY; VIDEO APPLICATIONS;

IMAGE CODING;

EID: 34548835459     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373404     Document Type: Conference Paper

References (5)

1. T. W. Chen, et al., "Architecture Design of H.264/AVC Decoder with Hybrid Task Pipelining for High Definition Videos," IEEE Proc. ISCAS, vol. 3, pp. 2931-2934, May, 2005.
2. C. C Lin, et al., "A 160kGate 4.5kB SRAM H.264 Video Decoder for HDTV Applications," ISSCC Dig. Tech. Papers, pp. 406-407, Feb., 2006.
3. T. M. Liu, et al., "A 125μW, Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications," ISSCC Dig. Tech. Papers, pp. 402-403, Feb., 2006.
4. Y. Hu, et al., "A High Definition H.264/AVC Hardware Video Decoder Core for Multimedia SoCs," Proc. ISCE, pp. 385-389, Sept., 2004.
5. H. Y. Kang, et al., "MPEG4 AVC/H.264 Decoder with Scalable Bus Architecture and Dual Memory Controller," Proc ISCAS, vol. 2, pp. 145-148, May, 2004.