Ultra-dynamic voltage scaling using sub-threshold operation and local voltage dithering in 90nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Calhoun, Benton H ^a   Chandrakasan, Anantha ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY POINT; TEST CHIPS; VOLTAGE DITHERING; VOLTAGE SCALING;

ELECTRIC POTENTIAL; ENERGY MANAGEMENT; MICROPROCESSOR CHIPS; THERMAL EFFECTS;

CMOS INTEGRATED CIRCUITS;

EID: 28144440165     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. V. Gutnik and A. Chandrakasan, "Embedded Power Supply for Low-Power DSP," IEEE Trans. on VLSI Systems, vol. 5, no. 4, pp. 425-435, Dec., 1997.
2. H. Kawaguchi et al., "A Controller LSI for Realizing VDD-Hopping Scheme with Off-the-Shelf Processors and Its Application to MPEG4 System," IEICE Trans. Electron., vol. E85- C, no.2, pp. 263-271, Feb., 2002.
3. A. Wang and A. Chandrakasan, "A 180mV FFT Processor Using Subthreshold Circuit Techniques," ISSCC Dig. Tech. Papers, pp. 292-293, Feb., 2004.
4. B. Calhoun and A. Chandrakasan, "Characterizing and Modeling Minimum Energy Operation for Subthreshold Circuits," ISLPED, pp. 90-95, 2004.