A 65nm Sub-Vt microcontroller with integrated SRAM and switched-capacitor DC-DC converter

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 318-320

  Kwong, Joyce ^a   Ramadass, Yogesh ^a   Verma, Naveen ^a   Koesler, Markus ^b   Huber, Korbinian ^b   Moormann, Hans ^b   Chandrakasan, Anantha ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b Texas Instruments Deutschland GmbH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

MICROCONTROLLERS; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEM-ON-CHIP;

CORE LOGIC; MINIMUM ENERGY; ON CHIPS; STANDBY POWER; SWITCHED-CAPACITOR DC-DC CONVERTER; TIMING METHODOLOGIES;

DC-DC CONVERTERS;

EID: 49549093629     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523185     Document Type: Conference Paper

References (5)

1. A. Wang and A. Chandrakasan, "A 180-mV Subthreshold FFT Processor Using a Minimum Energy Design Methodology," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 310-319, Jan. 2005.
2. B. Zhai, et al., "A 2.60pJ/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency," IEEE Symp. VLSI Circuits, pp. 154-155, June 2006.
3. J. Kwong and A. P. Chandrakasan, "Variation-Driven Device Sizing for Minimum Energy Sub-threshold Circuits," Int. Symp. on Low Power Electronics and Design, pp. 8-13, Oct. 2006.
4. t SRAM Employing Sense-Amplifier Redundancy" ISSCC Dig. Tech. Papers, pp. 328-329, Feb. 2007.
5. Y. K. Ramadass and A. P. Chandrakasan, "Voltage Scalable Switched Capacitor DC-DC Converter for Ultra-Low-Power On-Chip Applications," IEEE Power Electronics Specialists Conference, pp. 2353-2359, June 2007.