A 6b 0.2-to-0.9V highly digital flash ADC with comparator redundancy

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 554-556

  Daly, Denis C ^a   Chandrakasan, Anantha P ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPARATORS (OPTICAL); IIR FILTERS; REDUNDANCY;

CMOS PROCESSS; COMMON MODE REJECTIONS; FLASH-ADC; SUBTHRESHOLD;

COMPARATOR CIRCUITS;

EID: 49549085526     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523303     Document Type: Conference Paper

References (4)

1. M. P. Flynn, C. Donovan, and L. Sattler, "Digital Calibration Incorporating Redundancy of Flash ADCs," IEEE Trans. Circuits & Systems II, vol. 50, no. 5, pp. 205-213, May, 2003.
2. G. Van der Plas, S. Decoutere, and S. Donnay, "A 0.16pJ/conversion-step 2.5mW 1.25GS/s 4b ADC in a 90nm digital CMOS process," ISSCC Dig. Tech. Papers, pp. 566-567, Feb., 2006.
3. K. Pun, S. Chatterjee, and P. Kinget, "A 0.5V 74dB SNDR 25kHz CT ΔΣ Modulator with Return-to-Open DAC," ISSCC Dig. Tech. Papers, pp. 181-182, Feb., 2006.
4. A. Wang and A. P. Chandrakasan, "A 180-mV Subthreshold FFT Processor Using a Minimum Energy Design Methodology," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 310-319, Jan., 2005.