A 50-MS/s (35 mW) to 1-kS/s (15 μW) power scaleable 10-bit pipelined ADC using rapid power-on opamps and minimal bias current variation

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 12, 2005, Pages 2446-2455

  Ahmed, Imran ^a,b,c   Johns, David A ^a,b  

^a IEEE   (Canada)

^b UNIVERSITY OF TORONTO   (Canada)

^c Snowbush Microelectronics   (Canada)

Author keywords

ADC; Analog to digital conversion; CMOS; Low power; Pipeline; Power reduction; Power scaleable; Reconfigurable; Scaleable

Indexed keywords

LOW POWER; POWER REDUCTION; POWER SCALEABLE; SCALEABLE;

CMOS INTEGRATED CIRCUITS; MODULATION; OPERATIONAL AMPLIFIERS; SAMPLING;

ANALOG TO DIGITAL CONVERSION;

EID: 29044441000     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.856289     Document Type: Conference Paper

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