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Volumn , Issue , 2007, Pages 192-195

1.8mW, hybrid-pipelined H.264/AVC decoder for mobile devices

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER NETWORKS; DECODING; MOBILE DEVICES; MOTION COMPENSATION; PIPELINES; REUSABILITY; TELECOMMUNICATION EQUIPMENT;

EID: 51349093043     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2007.4425763     Document Type: Conference Paper
Times cited : (8)

References (12)
  • 1
    • 67649092274 scopus 로고    scopus 로고
    • T. Chen, Y.-W. Huang, T.-C. Chen, Y.-H. Chen, C.-Y. Tsai and L.-G. Chen, Architecture Design of H.264/AVC Decoder with Hybrid Task Pipelining of High Definition Videos, ISCAS, 2005.
    • T. Chen, Y.-W. Huang, T.-C. Chen, Y.-H. Chen, C.-Y. Tsai and L.-G. Chen, "Architecture Design of H.264/AVC Decoder with Hybrid Task Pipelining of High Definition Videos," ISCAS, 2005.
  • 3
    • 85165855922 scopus 로고    scopus 로고
    • T.-M. Liu, C.-C. Chung, C.-Y. Lee, L.-A. Lin, and S.-Z. Wang, Design of a 125uW, Fully-Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Application, DAC, 2006.
    • T.-M. Liu, C.-C. Chung, C.-Y. Lee, L.-A. Lin, and S.-Z. Wang, "Design of a 125uW, Fully-Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Application," DAC, 2006.
  • 4
    • 67649092274 scopus 로고    scopus 로고
    • To-Wei Chen, Yu-Wen Huang, Tung-Chien Chen, Yu-Han Chen, Chuan-Yung Tsai, and Liang-Gee Chen. Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos ISCAS, 2005.
    • To-Wei Chen, Yu-Wen Huang, Tung-Chien Chen, Yu-Han Chen, Chuan-Yung Tsai, and Liang-Gee Chen. "Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos" ISCAS, 2005.
  • 5
    • 4344691469 scopus 로고    scopus 로고
    • MPEG4 AVC/H.264 decoder with scalable bus architecture and dual memory controller
    • H. Y. Kang, K. A. Jeong, J. Y. Bae, Y. S. Lee, and S. H. Lee. "MPEG4 AVC/H.264 decoder with scalable bus architecture and dual memory controller" ISCAS, 2004.
    • (2004) ISCAS
    • Kang, H.Y.1    Jeong, K.A.2    Bae, J.Y.3    Lee, Y.S.4    Lee, S.H.5
  • 8
    • 33645001798 scopus 로고    scopus 로고
    • Fast 2-dimensional 4x4 forward integer transform implementation for H.264/AVC
    • C. P. Fan, "Fast 2-dimensional 4x4 forward integer transform implementation for H.264/AVC," IEEE Transactions on Circuits and Systems II, 2006.
    • (2006) IEEE Transactions on Circuits and Systems , vol.2
    • Fan, C.P.1
  • 11
    • 33847160386 scopus 로고    scopus 로고
    • Bandwidth Optimized Motion Compensation Hardware Design for H.264/AVC HDTV Decoder
    • C.Y. Tsai, T.C. Chen, T.W. Chen and L.G. Chen, "Bandwidth Optimized Motion Compensation Hardware Design for H.264/AVC HDTV Decoder", MWSCAS, 2005.
    • (2005) MWSCAS
    • Tsai, C.Y.1    Chen, T.C.2    Chen, T.W.3    Chen, L.G.4
  • 12
    • 67649227511 scopus 로고    scopus 로고
    • T. M. Liu, W. P. Lee, T. A. Lin and C. Y. Lee, A Memory-Efficient Deblocking Filter for H.264/AVC Video Coding, ISCAS, 2005.
    • T. M. Liu, W. P. Lee, T. A. Lin and C. Y. Lee, "A Memory-Efficient Deblocking Filter for H.264/AVC Video Coding", ISCAS, 2005.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.