A comparison study of symmetric ultrathin-body double-gate devices with metal source/drain and doped source/drain

IEEE Transactions on Electron Devices

Volumn 52, Issue 8, 2005, Pages 1859-1867

  Xiong, Shiying ^a   King, Tsu Jae ^a   Bokor, Jeffrey ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Double gate; Metal source drain (S D); Parasitic capacitance; Schottky barrier; Series resistance

Indexed keywords

CAPACITANCE; CHARGE CARRIERS; COMPUTER SIMULATION; ELECTRIC RESISTANCE; ELECTRON TUNNELING; GATES (TRANSISTOR); SCHOTTKY BARRIER DIODES; THRESHOLD VOLTAGE;

DOUBLE GATE; PARASITIC CAPACITANCE; SERIES RESISTANCE;

MOSFET DEVICES;

EID: 23344435702     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.852893     Document Type: Article

References (48)

1. Y. Taur, "An analytical solution to a double-gate MOSFET with undoped body," IEEE Electron Device Lett., vol. 21, pp. 245-247, May 2000.
2. Y. Taur, "Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs," IEEE Trans. Electron Devices, vol. 48, no. 12, pp. 2861-2869, Dec. 2001.
3. Y. Taur, X. Liang, W. Wang, and H. Lu, "A continuous, analytic drain-current model for DG MOSFETs," IEEE Electron Device Lett., vol. 25, no. 2, pp. 107-109, Feb. 2004.
4. L. Ge and J. G. Fossum, "Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs," IEEE Trans. Electron Devices, vol. 49, no. 2, pp. 287-294, Feb. 2002.
5. Q. Chen, B. Agrawal, and J. D. Meindl, "A comprehensive analytical subthreshold swing (S) model for double-gate MOSFETs," IEEE Trans. Electron Devices, vol. 49, no. 6, pp. 1086-1090, Jun. 2002.
6. + double-gate SOI MOSFETs," IEEE Trans. Electron Devices, vol. 43, no. 5, pp. 732-738, May 1996.
7. P. Francis, A. Terao, D. Flandre, and F. Van de Wiele, "Modeling of ultrathin double-gate nMOS/SOI transistors," IEEE Trans. Electron Devices, vol. 41, no. 5, pp. 715-720, May 1994.
8. T. Tanaka, K. Suzuki, H. Horie, and T. Sugii, "Ultrafast operation of Vth-adjusted p-n double-gate SOI MOSFETs," IEEE Electron Device Lett., vol. 15, no. 10, pp. 386-388, Oct. 1994.
9. H.-S. Wong, K. Chan, and Y. Taur, "Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel," in IEDM Tech. Dig., 1997, pp. 427-430.
10. J. H. Lee, G. Taraschi, A. Wei, T. A. Langdo, E. A. Fitzgerald, and D. A. Antoniadis, "Super self-aligned double-gate (SSDG) MOSFET's utilizing oxidation rate difference and selective epitaxy," in IEDM Tech. Dig., 1999, pp. 71-74.
11. E. Jones, M. Ieong, T. Kanarsky, O. Dokumaci, R. Roy, L. Shi, T. Furukawa, R. Miller, and H.-S. Wong, "High performance of planar double gate MOSFET's with thin backgate dielectrics," in Proc. Device Research Conf., 2001, pp. 28-29.
12. X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, "Sub 50-nm FinFET: PMOS," in IEDM Tech. Dig., 1999, pp. 67-70.
13. M. Ieong, E. C. Jones, T. Kanarsky, Z. Ren, O. Dokumaci, R. A. Roy, L. Shi, T. Furukawa, Y. Taur, R. J. Miller, and H.-S. P. Wong, "Experimental evaluation of carrier transport and device design for planar symmetric/asymmetric double-gate/ground-plane CMOSFETs," in IEDM Tech. Dig., Dec. 2001, pp. 441-444.
14. S. Harrison, P. Coronel, F. Leverd, R. Cerutti, R. Palla, D. Delille, S. Borel, S. Jullian, R. Pantel, S. Descombes, D. Dutartre, Y. Morand, M. P. Samson, D. Lenoble, A. Talbot, A. Villaret, S. Monfray, P. Mazoyer, J. Bustos, H. Brut, A. Cros, D. Munteanu, J.-L. Autran, and T. Skotnicki, "Highly performant double gate MOSFET realized with SON process electron devices meeting," in IEDM Tech. Dig., Dec. 2003, pp. 449-452.
15. Y.-K. Choi, T-J. King, and C. Hu, "Nanoscale CMOS spacer FinFET for the terabit era," IEEE Electron Device Lett., vol. 3, pp. 25-27, Jan. 2002.
16. J. Kedzierski, D. M. Fried, E. J. Nowak, T. Kanarsky, J. H. Rankin, H. Hanafi, W. Natzle, D. Boyd, Y. Zhang, R. A. Roy, J. Newbury, C. Yu, Q. Yang, P. Saunders, C. P. Willets, A. Johnson, S. P. Cole, H. E. Young, N. Carpenter, D. Rakowski, B. A. Rainey, P. E. Cottrell, M. Ieong, and H.-S. P. Wong, "High-performance symmetric-gate and CMOS- compatible Vt asymmetric-gate FinFET devices," in IEDM Tech. Dig., Dec. 2001, pp. 437-440.
17. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, C. Hu, M.-R. Lin, and D. Kyser, "FinFET scaling to 10 nm gate length," in IEDM Tech. Dig., Dec. 2002, pp. 251-254.
18. E. J. Nowak, B. A. Rainey, D. M. Fried, J. Kedzierski, M. Ieong, W. Leipold, J. Wright, and M. Breitwisch, "A functional FinFET-DGCMOS SRAM cell," in IEDM Tech. Dig., Dec. 2002, pp. 411-414.
19. M. Masahara, T. Matsukawa, K. Ishii, Y. Liu, H. Tanoue, K. Sakamoto, T. Sekigawa, H. Yamauchi, S. Kanemaru, and E. Suzuki, "15-nm-thick Si channel wall vertical double-gate MOSFET," in IEDM Tech. Dig., Dec. 2002, pp. 949-951.
20. Y. X. Liu, M. Masahara, K. Ishii, T. Tsutsumi, S. Sekigawa, H. Takashima, H. Yamauchi, and E. Suzuki, "Flexible threshold voltage FinFET's with independent double gates and an ideal rectangular cross section Si-Fin channel," in IEDM Tech. Dig., Dec. 2003, pp. 986-988.
21. S. Harrison, P. Coronel, F. Leverd, R. Cerutti, R. Palla, D. Delille, S. Borel, S. Jullian, R. Pantel, S. Descombes, D. Dutartre, Y. Morand, M. P. Samson, D. Lenoble, A. Talbot, A. Villaret, S. Monfray, P. Mazoyer, J. Bustos, H. Brut, A. Cros, D. Munteanu, J.-L. Autran, and T. Skotnicki, "Highly performant double gate MOSFET realized with SON process electron devices meeting," in IEDM Tech. Dig., Dec. 2003, pp. 449-452.
22. P. Ranade, Y.-K. Choi, D. Ha, A. Agarwal, M. Ameen, and T.-J. King, "Tunable-work-function Molybdenum gate technology for FD-SOICMOS," in IEDM Tech. Dig., Dec. 2002, pp. 363-366.
23. International Technology Roadmap for Semiconductors (ITRS) (2003). [Online]. Available: http://public.itrs.net
24. D. Esseni, A. Abramo, L. Selmi, and E. Sangiorgi, "Physically based modeling of low field electron mobility in ultrathin single- and double-gate SOI n-MOSFETs," IEEE Trans. Electron Devices, vol. 50, no. 12, pp. 2445-2455, Dec. 2003.
25. A. Khakifirooz and D. A. Antoniadis, "On the electron mobility in ultrathin SOI and GOI," IEEE Electron Device Lett., vol. 25, no. 2, pp. 80-82, Feb. 2004.
26. D. Esseni, M. Mastrapasqua, G. K. Celler, C. Fiegna, L. Selmi, and E. Sangiorgi, "An experimental study of mobility enhancement in ultrathin SOI transistors operated in double-gate mode," IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 802-808, Mar. 2003.
27. M. Shoji and S. Horiguchi, "Electronic structures and phonon limited electron mobility of double-gate silicon-on-insulator Si inversion layers," J. Appl. Phys., vol. 85, pp. 2722-2731, May 1999.
28. M. Shoji and S. S. Horiguchi, "Phononlimited inversion layer electron mobility in extremely thin Si layer of silicon-on-insulator metal-oxide-semiconductor field-effect transistor," J. Appl. Phys., vol. 82, pp. 6096-6101, Dec. 1997.
29. K. Uchida, H. Watanabe, A. Kinoshita, J. Koga, T. Numata, and S. Takagi, "Experimental study on carrier transport mechanism in ultrathin-body SOI n- and p-MOSFET's with SOI thickness less than 5 nm," in IEDM Tech. Dig., Dec. 2002, pp. 47-50.
30. 2 interfaces in fully depleted silicon-on-insulator inversion layers," J. Appl. Phys., vol. 86, pp. 6854-6863, Dec. 15, 1999.
31. S. Xiong and J. Bokor, "Sensitivity of double-gate and FinFET Devices to process variations," IEEE Trans. Electron Devices, vol. 50, no. 11, pp. 2255-2261, Nov. 2003.
32. G. Bersuker, P. Zeitzoff, G. Brown, and H. R. Huff, "Dielectrics for future transistors," Mater Today, vol. 7, pp. 26-33, Jan. 2004.
33. B. Cheng, M. Cao, P. V. Voorde, W. Greene, H. Stork, Z. Yu, and J. C. S. Woo, "Design consideration of high-κ gate dielectrics for Sub-0.1 μm MOSFETs," IEEE Trans. Electron Devices, vol. 46, no. 1, pp. 261-262, Jan. 1999.
34. S. Xiong and J. Bokor, "Structural optimization of SUTBDG devices for low-power applications," IEEE Trans. Electron Devices, vol. 52, pp. 360-366, Mar. 2005.
35. B. Pellegrini, "Properties of silicon-metal contacts versus metal work-function, silicon impurity concentration and bias voltage," J. Phys. D: Appl. Phys., vol. 9, pp. 55-68, 1976.
36. C. Wang, J. P. Snyder, and J. R. Tucker, "Sub-40 nm PtSi Schottky source/drain metal-oxide-semiconductor field-effect transistors," Appl. Phys. Lett., vol. 74, pp. 1174-1176, Feb. 1999.
37. T = 281) GHz," IEEE Electron Device Lett., vol. 25, no. 4, pp. 220-222, Apr. 2004.
38. M. Tao, D. Udeshi, N. Basit, E. Maldonado, and W. P. Kirk, "Removal of dangling bonds and surface states on silicon (001) with a monolayer of selenium," Appl. Phys. Lett., vol. 82, pp. 1559-1561, Mar. 2003.
39. M. Tao, S. Agarwal, D. Udeshi, N. Basit, E. Maldonado, and W. P. Kirk, "Low Schottky barriers on n-type silicon (001)," Appl. Phys. Lett., vol. 83, pp. 2593-2595, Sep. 2003.
40. M. Tao, D. Udeshi, S. Agarwal, E. Maldonado, and W. P. Kirk, "Negative Schottky barrier between titanium and n-type Si (001) for low-resistance ohmic contacts," Solid State Electron., vol. 48, pp. 335-338, Feb. 2004.
41. D. Connelly, C. Faulkner, D. E. Grupp, and J. S. Harris, "A new route to zero-barrier metal source/drain MOSFETs," IEEE Trans. Nanotech., vol. 3, no. 3, pp. 98-104, Mar. 2004.
42. A. Kinoshita, Y. Tsuchiya, A. Yagishita, K. Uchida, and J. Koga, "Solution for high-performance Schottky-source/drain MOSFETs: Schottky barrier height engineering with dopant segregation technique," in VLSI Tech. Dig., 2004, pp. 168-169.
43. J. Guo and M. S. Lundstrom, "A computational study of thin-body, double-gate, Schottky barrier MOSFETs," IEEE Trans. Electron Devices, vol. 49, no. l 1, pp. 1897-1902, Nov. 2002.
44. C. R. Crowell, "Richardson constant and tunneling effective mass for thermionic and thermionic-field emission in Schottky barrier diodes," Solid State Electron., vol. 12, pp. 55-59, 1969.
45. V. L. Rideout and C. R. Crowell, "Effects of image force and tunneling on current transport in metal-semiconductor (Schottky barrier) contacts," Solid State Electron., vol. 13, pp. 993-1009, 1970.
46. J. M. Andrews and M. P. Lepselter, "Reverse current-voltage characteristics of metal-silicide Schottky diodes," Solid State Electron., vol. 13, pp. 1011-1023, 1970.
47. P. DE Visschere, "Image forces and MIS Schottky barriers," Solid State Electron., vol. 29, no. 9, p. 813 475, 1986.
48. D. Connelly, C. Faulkner, and D. E. Grupp, "Performance advantage of Schottky source/drain in ultrathin-body silicon-on-insulator and dual-gate CMOS," IEEE Trans. Electron Devices, vol. 50, pp. 1340-1345, May 2003.